EP1S40F1020I6 Altera, EP1S40F1020I6 Datasheet - Page 88
EP1S40F1020I6
Manufacturer Part Number
EP1S40F1020I6
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40F1020I6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1862
EP1S40F1020I6
EP1S40F1020I6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S40F1020I6
Manufacturer:
NEC
Quantity:
9 760
Company:
Part Number:
EP1S40F1020I6
Manufacturer:
ALTERA40
Quantity:
140
Part Number:
EP1S40F1020I6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
PLLs & Clock Networks
2–74
Stratix Device Handbook, Volume 1
There are 16 dedicated clock pins (CLK[15..0]) to drive either the global
or regional clock networks. Four clock pins drive each side of the device,
as shown in
the global and regional clock networks.
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. The global clock networks can be used as clock sources for all
resources within the device—IOEs, LEs, DSP blocks, and all memory
blocks. These resources can also be used for control signals, such as clock
enables and synchronous or asynchronous clears fed from the external
pin. The global clock networks can also be driven by internal logic for
internally generated global clocks and asynchronous clears, clock
enables, or other control signals with large fanout.
16 dedicated CLK pins driving global clock networks.
Figure
2–42. Enhanced and fast PLL outputs can also drive
Figure 2–42
Altera Corporation
shows the
July 2005