EP1S40F1020C5 Altera, EP1S40F1020C5 Datasheet - Page 4
EP1S40F1020C5
Manufacturer Part Number
EP1S40F1020C5
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40F1020C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2089
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EP1S40F1020C5
Manufacturer:
XILINK
Quantity:
5 510
Company:
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA30
Quantity:
113
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S40F1020C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S40F1020C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Stratix Device Family Data Sheet
Section I–4
Chapter
4
September 2004, v3.1
January 2005, 3.2
Date/Version
●
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●
Updated rise and fall input values.
Updated Note 3 in
Updated
Updated
page
Updated
page
Updated
Updated description of
Updated
Added signals t
Added rows t
page
Added rows t
Updated Note 2 in
Added rows t
page
Updated
Updated
4–13. Added rows V
4–15.
4–24.
4–25.
Table 4–10 on page
Table 4–20 on page 4–12
Table 4–26 on page 4–14
Table 4–31 on page
Table 4–36 on page
Table 4–46 on page
Table 4–47 on page
M512CLKENSU
M4CLKENSU
MRAMCLKENSU
OUTCO
Table 4–8 on page
Table 4–54 on page
, T
“External Timing Parameters” on page
and t
XZ
Changes Made
and t
, and T
IL(AC)
and t
M4CLKENH
4–6.
4–16.
4–20.
4–29.
4–29.
M512CLKENH
and V
MRAMCLKENH
Stratix Device Handbook, Volume 1
ZX
through
through
to
IH(AC)
to
Figure 4–4 on page
4–4.
4–35.
Table 4–41 on page
to
to each table.
to
Table 4–23 on
Table 4–29 on
Table 4–40 on
Table 4–42 on
Altera Corporation
4–33.
4–24.
4–33.