EP1S40F1020C5 Altera, EP1S40F1020C5 Datasheet - Page 71
EP1S40F1020C5
Manufacturer Part Number
EP1S40F1020C5
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40F1020C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2089
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EP1S40F1020C5
Manufacturer:
XILINK
Quantity:
5 510
Company:
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA30
Quantity:
113
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S40F1020C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S40F1020C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–32. Multiplier Sub-Block within Stratix DSP Block
Note to
(1)
Altera Corporation
July 2005
These signals can be unregistered or registered once to match data path pipelines if required.
Figure
Data B
Data A
2–32:
shiftout B
shiftin B
shiftout A
The DSP block consists of the following elements:
■
■
Multiplier Block
The DSP block multiplier block consists of the input registers, a
multiplier, and pipeline register for pipelining multiply-accumulate and
multiply-add/subtract functions as shown in
ENA
ENA
D
D
Multiplier block
Adder/output block
CLRN
CLRN
clock[3..0]
sign_a (1)
sign_b (1)
shiftin A
aclr[3..0]
ena[3..0]
Q
Q
ENA
D
CLRN
Q
Stratix Device Handbook, Volume 1
Figure
Optional
Multiply-Accumulate
and Multiply-Add
Pipeline
Result
to Adder
blocks
2–32.
Stratix Architecture
2–57