EP2S90F1020C5N Altera, EP2S90F1020C5N Datasheet - Page 24

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EP2S90F1020C5N

Manufacturer Part Number
EP2S90F1020C5N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C5N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1918
EP2S90F1020C5N

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Adaptive Logic Modules
2–16
Stratix II Device Handbook, Volume 1
Figure 2–12. Conditional Operation Example
The arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, add/subtract control, synchronous clear,
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals are good candidates for the inputs
that are shared between the four LUTs in the ALM. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. The Quartus II software automatically places any
registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. Carry chains can begin in
either the first ALM or the fifth ALM in an LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
Carry Chain
syncdata
X[0]
X[1]
X[2]
Y[0]
Y[1]
Y[2]
ALM 1
ALM 2
Comb &
Comb &
Comb &
Comb &
Adder
Adder
Adder
Adder
Logic
Logic
Logic
Logic
X[2]
X[0]
X[1]
Adder output
is not used.
syncload
syncload
syncload
D
D
D
reg0
reg1
reg0
carry_out
Q
Q
Q
R[0]
R[1]
R[2]
Altera Corporation
To general or
local routing
To general or
local routing
To general or
local routing
To local routing &
then to LAB-wide
syncload
May 2007

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