EP2S90F1020C5 Altera, EP2S90F1020C5 Datasheet - Page 118

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EP2S90F1020C5

Manufacturer Part Number
EP2S90F1020C5
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C5

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1465
EP2S90F1020C5

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0
SignalTap II Embedded Logic Analyzer
SignalTap II
Embedded Logic
Analyzer
Configuration
3–4
Stratix II Device Handbook, Volume 1
f
For more information on JTAG, see the following documents:
Stratix II devices feature the SignalTap II embedded logic analyzer, which
monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
The logic, circuitry, and interconnects in the Stratix II architecture are
configured with CMOS SRAM elements. Altera
reconfigurable and every device is tested with a high coverage
production test program so you do not have to perform fault testing and
can instead focus on simulation and design verification.
Stratix II devices are configured at system power-up with data stored in
an Altera configuration device or provided by an external controller (e.g.,
a MAX
using the fast passive parallel (FPP), active serial (AS), passive serial (PS),
passive parallel asynchronous (PPA), and JTAG configuration schemes.
The Stratix II device’s optimized interface allows microprocessors to
configure it serially or in parallel, and synchronously or asynchronously.
The interface also enables microprocessors to treat Stratix II devices as
memory and configure them by writing to a virtual memory location,
making reconfiguration easy.
In addition to the number of configuration methods supported, Stratix II
devices also offer the design security, decompression, and remote system
upgrade features. The design security feature, using configuration
bitstream encryption and AES technology, provides a mechanism to
protect your designs. The decompression feature allows Stratix II FPGAs
to receive a compressed configuration bitstream and decompress this
data in real-time, reducing storage requirements and configuration time.
The remote system upgrade feature allows real-time system upgrades
from remote locations of your Stratix II designs. For more information,
see
“Configuration Schemes” on page
The IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing for Stratix II &
Stratix II GX Devices chapter of the Stratix II Device Handbook,
Volume 2 or the Stratix II GX Device Handbook, Volume 2
Jam Programming & Test Language Specification
®
II device or microprocessor). Stratix II devices can be configured
3–7.
®
FPGA devices are
Altera Corporation
May 2007
®

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