EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 129
EP2SGX90EF1152C4N
Manufacturer Part Number
EP2SGX90EF1152C4N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C4N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1767
EP2SGX90EF35C4NES
EP2SGX90EF35C4NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
Quantity:
648
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Figure 2–84. Stratix II GX IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
(3)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–84:
clkout
aclr/apreset
sclr/spreset
ce_out
oe
Chip-Wide Reset
Output Register
Output Register
OE Register
OE Register
ENA
CLRN/PRN
CLRN/PRN
CLRN/PRN
CLRN/PRN
D
ENA
D
ENA
D
ENA
D
Q
Q
Q
Q
Used for
DDR, DDR2
SDRAM
Notes
clk
Stratix II GX Device Handbook, Volume 1
Open-Drain Output
Drive Strength
Pin Delay
(1),
Output
Control
(2)
OE Register
t CO Delay
Stratix II GX Architecture
V CCIO
V CCIO
PCI Clamp (3)
Termination
On-Chip
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
2–121
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