EP2S90F1020C3N Altera, EP2S90F1020C3N Datasheet - Page 179
EP2S90F1020C3N
Manufacturer Part Number
EP2S90F1020C3N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1020C3N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
816.99MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S90F1020C3N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 179 of 238
- Download datasheet (3Mb)
Altera Corporation
April 2011
t
t
t
t
t
t
t
t
t
t
t
t
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
Table 5–47. EP2S15 Row Pins Global Clock Timing Parameters
Table 5–48. EP2S30 Column Pins Regional Clock Timing Parameters
Table 5–49. EP2S30 Column Pins Global Clock Timing Parameters
Parameter
Parameter
Parameter
Industrial
Industrial
Industrial
-0.125
-0.043
-0.056
1.206
1.211
1.553
1.396
0.114
1.539
1.382
0.101
-0.12
Minimum Timing
Minimum Timing
Minimum Timing
EP2S30 Clock Timing Parameters
Tables 5–48
for EP2S30 devices.
Commercial
Commercial
Commercial
-0.138
-0.133
-0.052
-0.067
1.262
1.267
1.627
1.462
0.113
1.613
1.448
0.098
through
5–51
-3 Speed
-3 Speed
-3 Speed
Grade
-0.023
-0.027
Grade
-0.017
Grade
-0.033
2.113
2.109
show the maximum clock timing parameters
2.639
2.397
0.225
2.622
2.380
0.209
Stratix II Device Handbook, Volume 1
-4 Speed
-4 Speed
-4 Speed
Grade
-0.038
-0.042
Grade
Grade
-0.049
2.422
2.418
3.025
2.747
0.248
3.008
2.730
0.229
-0.03
DC & Switching Characteristics
-5 Speed
-5 Speed
-5 Speed
Grade
-0.056
-0.061
Grade
-0.044
Grade
-0.057
2.815
2.810
3.509
3.185
3.501
3.177
0.267
0.28
Unit
Unit
Unit
5–43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Related parts for EP2S90F1020C3N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: