EP2S90F1020C3N Altera, EP2S90F1020C3N Datasheet - Page 19

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EP2S90F1020C3N

Manufacturer Part Number
EP2S90F1020C3N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C3N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
816.99MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S90F1020C3N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S90F1020C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S90F1020C3N
Manufacturer:
ALTERA
0
Figure 2–7. ALM in Normal Mode
Note to
(1)
Altera Corporation
May 2007
datae0
datae1
datae0
datae1
datae0
datae1
dataf0
dataf1
dataf0
dataf1
dataf0
dataf1
dataa
datab
datad
datac
dataa
datab
datad
datac
dataa
datab
datad
datac
Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of
functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc.
Figure
2–7:
3-Input
LUT
4-Input
5-Input
5-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
LUT
The normal mode provides complete backward compatibility with four-
input LUT architectures. Two independent functions of four inputs or less
can be implemented in one Stratix II ALM. In addition, a five-input
function and an independent three-input function can be implemented
without sharing inputs.
Note (1)
combout0
combout1
combout0
combout1
combout0
combout1
datae0
datae1
datae0
datae0
datae1
dataf0
dataf1
dataf0
dataf0
dataf1
dataa
datab
datad
dataa
datab
datad
dataa
datab
datad
datac
datac
datac
Stratix II Device Handbook, Volume 1
6-Input
6-Input
6-Input
5-Input
5-Input
LUT
LUT
LUT
LUT
LUT
Stratix II Architecture
combout0
combout1
combout0
combout0
combout1
2–11

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