EP1S80F1020C5N Altera, EP1S80F1020C5N Datasheet - Page 257
EP1S80F1020C5N
Manufacturer Part Number
EP1S80F1020C5N
Description
IC STRATIX FPGA 80K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S80F1020C5N
Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
79040
# I/os (max)
773
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
79040
Ram Bits
7427520
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S80F1020C5N
Manufacturer:
ALTERA20
Quantity:
403
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High-Speed I/O
Specification
Altera Corporation
January 2006
t
f
t
t
Timing unit interval (TUI)
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t
t
J
W
C
HSCLK
RISE
FALL
HSDR
DUTY
LOCK
Table 4–124. High-Speed Timing Specifications & Terminology
High-Speed Timing Specification
Table 4–124
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Maximum LVDS data transfer rate (f
The timing difference between the fastest and slowest output edges,
including t
measurement.
The period of time during which the data must be valid to be captured
correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = t
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Deserialization factor (width of internal data bus).
PLL multiplication factor.
provides high-speed timing specifications definitions.
SW
CO
(max) – t
variation and clock skew. The clock is included in the TCCS
SW
(min).
C
/w).
Terminology
Stratix Device Handbook, Volume 1
HSDR
DC & Switching Characteristics
= 1/TUI).
4–87
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