XCS30XL-4VQ100I Xilinx Inc, XCS30XL-4VQ100I Datasheet - Page 38

• Manufacturer Part Number: XCS30XL-4VQ100I
• Description: IC FPGA 3.3V I-TEMP HP 100VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS30XL-4VQ100I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 77
• Number Of Gates: 30000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan and Spartan-XL FPGA Families Data Sheet
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfering
with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Although readback can be performed while the device is
operating, for best results and to freeze a known capture
state, it is recommended that the clock inputs be stopped
until readback is complete.
Readback of Spartan-XL family Express mode bitstreams
results in data that does not resemble the original bitstream,
because the bitstream format differs from other modes.
Spartan/XL FPGA Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, instantiate the
READBACK library symbol and attach the appropriate pad
symbols, as shown in
After Readback has been initiated by a Low-to-High transi-
tion on RDBK.TRIG, the RDBK.RIP (Read In Progress) out-
put goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit (Low)
38
Figure
32.
Default is CCLK
If Unconnected,
READ_TRIGGER
Figure 32: Readback Example
IBUF
TRIG
www.xilinx.com
CLK
READBACK
of the first frame. The first two data bits of the first frame are
always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
Readback Options
Readback options are: Readback Capture, Readback
Abort, and Clock Select. They are set with the bitstream
generation software.
Readback Capture
When the Readback Capture option is selected, the data
stream includes sampled values of CLB and IOB signals.
The rising edge of RDBK.TRIG latches the inverted values
of the four CLB outputs, the IOB output flip-flops and the
input signals I1 and I2. Note that while the bits describing
configuration (interconnect, function generators, and RAM
content) are not inverted, the CLB and IOB output signals
are inverted. RDBK.TRIG is located in the lower-left corner
of the device.
When the Readback Capture option is not selected, the val-
ues of the capture bits reflect the configuration data origi-
nally written to those memory locations. If the RAM
capability of the CLBs is used, RAM data are available in
Readback, since they directly overwrite the F and G func-
tion-table configuration of the CLB.
DATA
RIP
OBUF
READ_DATA
DS060_31_080400
DS060 (v1.8) June 26, 2008
Product Specification
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