XC6SLX25T-2CSG324C Xilinx Inc, XC6SLX25T-2CSG324C Datasheet - Page 10

• Manufacturer Part Number: XC6SLX25T-2CSG324C
• Description: IC FPGA SPARTAN 6 24K 324CSGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXTr

Specifications of XC6SLX25T-2CSG324C

• Number Of Logic Elements/cells: 24051
• Number Of Labs/clbs: 1879
• Total Ram Bits: 958464
• Number Of I /o: 190
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-LFBGA, CSPBGA
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision History
The following table shows the revision history for this document:
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DS160 (v1.7) March 21, 2011
Preliminary Product Specification
02/02/09
05/05/09
06/24/09
11/05/09
03/03/10
08/02/10
11/05/10
03/21/11
Date
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Initial Xilinx release.
Updated and simplified
banks, and
only for the 33 MHz specification. Revised number of logic cells, slices, and maximum user I/O, and
added number of flip-flops to
the CSG225 package and the XC6SLX45T in the FGG676 package, added XC6SLX9 in the FT(G)256
package and XC6SLX45 in the CSG324 package, and added notes. Clerical edits to the following
sections: Dynamic Reconfiguration Port, Readback,
PLL,
and electrical characteristics in the
Updated device/package combinations in
XC6SLX75T devices. Added ordering information and FPGA documentation sections. Removed
partial reconfiguration discussion from the
Updated
I/O numbers in
Processing—DSP48A1
Updated the slice counts for the LX25 and LX25T in
Port section. Added to the
frequency to 1080 MHz and the DSP48A1 slice maximum frequency to 320 MHz due to the addition
of the -4 speed specification. Clarified configurations in the
Updated
Updated data transfer rate per differential I/O from 1,050 Mb/s to 1,080 Mb/s in
FPGA
including
section with SPI and BPI interface information. Removed the Dynamic Reconfiguration Port section.
Updated the operating speed of the DSP48A1 slice multiplier and accumulator to 390 MHz in
Signal Processing—DSP48A1
In
transceiver data rate to 3.2 Gb/s. Updated the notes in
Automotive FPGA Family Overview to the
Updated from Advance to Preliminary Production Specification. Removed -4 speed grade from
Summary of Spartan-6 FPGA Features
Block for PCI Express Designs
Summary of Spartan-6 FPGA Features
Programmable Data
Features. Added the -3N speed grade to appropriate section throughout the document,
Figure 1, page 9
Low-Power Gigabit Transceiver
Figure
Integrated Memory Controller blocks
Table
1. Updated category in
1and
Designed for low
Slice, Input/Output, and PCI Express documentation.
to show -4 speed grade. Added 64-bit PCI support on
Width, and
www.xilinx.com
Spread-Spectrum Clocking
Table
Table
Slice. Updated
and
2. Clarifying edits to these sections: Configuration,
Input/Output
1. In
Input and Output
Description of Revisions
Memory Controller
and
Table 2
Table
operating rate.
cost,
Table 1
and in
Spartan-6 FPGA
Readback
Figure 1
2, revised user I/O counts, removed the XC6SLX25 in
Input and Output
Multi-voltage, multi-standard SelectIO™ interface
sections on
from Size to Body Size. Updated the
section.
Low-Power Gigabit
and
CLBs, Slices, and
Table
per XCN11008. Updated
Delay.
section.
Table 2
section. Changed the PLL VCO maximum
Figure
Block. Clarified I/O pin range, V
1. Revised the Dynamic Reconfiguration
Programmable Data Width
Documentation.
page
including adding the XC6SLX75 and
1. Added
Delay.
1. Clarified PCI support on
Transceiver, updated GTP serial
Spartan-6 Family Overview
LUTs,
DS170
Frequency
Summary of Spartan-6
page
Integrated Endpoint
, XA Spartan-6
Digital Signal
1. Updated User
Configuration
section.
REF
Synthesis,
page
banks,
Digital
1is
10