XCV50-6TQ144C Xilinx Inc, XCV50-6TQ144C Datasheet

IC FPGA 2.5V C-TEMP 144-TQFP

XCV50-6TQ144C

Manufacturer Part Number
XCV50-6TQ144C
Description
IC FPGA 2.5V C-TEMP 144-TQFP
Manufacturer
Xilinx Inc
Series
Virtex™r
Datasheet

Specifications of XCV50-6TQ144C

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
384
Total Ram Bits
32768
Number Of I /o
98
Number Of Gates
57906
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Case
TQFP144
Dc
03+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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DS003-1 (v2.5 ) April 2, 2001
Features
Table 1: Virtex Field-Programmable Gate Array Family Members
DS003-1 (v2.5 ) April 2, 2001
Product Specification
XCV1000
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
Device
XCV50
Fast, high-density Field-Programmable Gate Arrays
-
-
-
-
Multi-standard SelectIO™ interfaces
-
-
Built-in clock-management circuitry
-
-
Hierarchical memory system
-
-
-
Flexible architecture that balances speed and density
-
-
-
-
-
-
-
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Densities from 50k to 1M system gates
System performance up to 200 MHz
66-MHz PCI Compliant
Hot-swappable for Compact PCI
16 high-performance interface standards
Connects directly to ZBTRAM devices
Four dedicated delay-locked loops (DLLs) for
advanced clock control
Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
System Gates
1,124,022
108,904
164,674
236,666
322,970
468,252
661,111
888,439
57,906
R
CLB Array
16x24
20x30
24x36
28x42
32x48
40x60
48x72
56x84
64x96
Logic Cells
10,800
15,552
21,168
27,648
1,728
2,700
3,888
5,292
6,912
0
0
www.xilinx.com
1-800-255-7778
0
Virtex™ 2.5 V
Field Programmable Gate Arrays
Product Specification
Description
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 µm CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
Available I/O
Maximum
Supported by FPGA Foundation™ and Alliance
Development Systems
-
-
SRAM-based in-system configuration
-
-
0.22 µm 5-layer metal process
100% factory tested
180
180
260
284
316
404
512
512
512
Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
Wide selection of PC and workstation platforms
Unlimited re-programmability
Four programming modes
Block RAM
114,688
131,072
32,768
40,960
49,152
57,344
65,536
81,920
98,304
Bits
SelectRAM+™ Bits
Table
Maximum
153,600
221,184
301,056
393,216
24,576
38,400
55,296
75,264
98,304
1.
Module 1 of 4
1

Related parts for XCV50-6TQ144C

XCV50-6TQ144C Summary of contents

Page 1

... Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode Table 1: Virtex Field-Programmable Gate Array Family Members Device System Gates XCV50 57,906 XCV100 108,904 XCV150 164,674 XCV200 236,666 XCV300 322,970 XCV400 ...

Page 2

Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Architecture Virtex devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) sur- rounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, ...

Page 3

... R Virtex Device/Package Combinations and Maximum I/O Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) Package XCV50 XCV100 CS144 94 94 TQ144 98 98 PQ240 166 166 HQ240 BG256 180 180 BG352 BG432 BG560 FG256 176 176 FG456 FG676 FG680 Virtex Ordering Information ...

Page 4

Virtex™ 2.5 V Field Programmable Gate Arrays Revision History Date Version 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 ...

Page 5

R DS003-2 (v2.8.1) December 9, 2002 Architectural Description Virtex Array The Virtex user-programmable gate array, shown in Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for ...

Page 6

Virtex™ 2.5 V Field Programmable Gate Arrays TCE OCE CLK ICE Table 1: Supported Select I/O Standards I/O Standard LVTTL 2 – LVCMOS2 PCI PCI, 3.3 ...

Page 7

R Input Path A buffer In the Virtex IOB input path routes the input signal either directly to internal logic or through an optional input flip-flop. An optional delay element at the D-input of this flip-flop elim- inates pad-to-pad hold ...

Page 8

Virtex™ 2.5 V Field Programmable Gate Arrays more I/O pins convert to V pins. Since these are always REF a superset of the V pins used for smaller devices REF possible to design a PCB that permits migration ...

Page 9

... Each memory block is four CLBs high, and conse- quently, a Virtex device 64 CLBs high contains 16 memory blocks per column, and a total of 32 blocks. Table 3 shows the amount of block SelectRAM memory that is available in each Virtex device. Table 3: Virtex Block SelectRAM Amounts Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 Routing, page 7 ...

Page 10

Virtex™ 2.5 V Field Programmable Gate Arrays Each block SelectRAM cell, as illustrated in fully synchronous dual-ported 4096-bit RAM with indepen- dent control signals for each port. The data widths of the two ports can be configured independently, providing built-in ...

Page 11

R General Purpose Routing Most Virtex signals are routed on the general purpose rout- ing, and consequently, the majority of interconnect resources are associated with this level of the routing hier- archy. The general routing resources are located in horizon- ...

Page 12

Virtex™ 2.5 V Field Programmable Gate Arrays Four dedicated clock pads are provided, one adjacent to each of the global buffers. The input to the global buffer is Global Clock Rows Delay-Locked Loop (DLL) Associated with each global clock input ...

Page 13

R In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA, and also to read back the configuration data. Figure diagram of the Virtex Series boundary scan logic. It ...

Page 14

... Virtex family the number of CLB rows (ranges from 010h for XCV50 to 040h for XCV1000 the company code (49h for Xilinx) The USERCODE register is supported. By using the USER- CODE, a user-programmable identification code can be loaded and shifted out for examination ...

Page 15

R with a common user interface regardless of their choice of entry and verification tools. The XDM software simplifies the selection of implementation options with pull-down menus and on-line help. Application programs ranging from schematic capture to Placement and Routing ...

Page 16

Virtex™ 2.5 V Field Programmable Gate Arrays Configuration Virtex devices are configured by loading configuration data into the internal configuration memory. Some of the pins used for this are dedicated configuration pins, while others can be re-used as general purpose ...

Page 17

R Table 8: Master/Slave Serial Mode Programming Switching Description DIN setup/hold, slave mode DIN setup/hold, master mode DOUT High time CCLK Low time Maximum Frequency Frequency Tolerance, master mode with respect to nominal MASTER Optional Pull-up 1 ...

Page 18

Virtex™ 2.5 V Field Programmable Gate Arrays Master-Serial Mode In master-serial mode, the CCLK output of the FPGA drives a Xilinx Serial PROM that feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK ...

Page 19

R FPGA starts to clear configuration memory. FPGA makes a final clearing pass and releases Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error CRC errors found, FPGA enters start-up phase causing DONE ...

Page 20

Virtex™ 2.5 V Field Programmable Gate Arrays 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance will ...

Page 21

R FPGA starts to clear configuration memory. FPGA makes a final clearing pass and releases Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error. first FPGAs enter start-up phase later FPGAs enter start-up phase When ...

Page 22

Virtex™ 2.5 V Field Programmable Gate Arrays CCLK CS WRITE DATA[0:7] BUSY Figure 18: SelectMAP Write Abort Waveforms Boundary-Scan Mode In the boundary-scan mode, configuration is done through the IEEE 1149.1 Test Access Port. Note that the PROGRAM pin must ...

Page 23

... For more detailed infor- mation, see application note XAPP151 “Virtex Configura- tion Architecture Advanced Users Guide”. Table 11: Virtex Bit-Stream Lengths Device # of Configuration Bits XCV50 XCV100 XCV150 1,040,096 XCV200 1,335,840 XCV300 1,751,808 ...

Page 24

Virtex™ 2.5 V Field Programmable Gate Arrays Date Version 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New ...

Page 25

... Table 1 correlates the current status of each Virtex device with a corresponding speed file designation. Table 1: Virtex Device Speed Grade Designations Speed Grade Designations Device Advance XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All specifications are subject to change without notice. ...

Page 26

Virtex™ 2.5 V Field Programmable Gate Arrays Virtex DC Characteristics Absolute Maximum Ratings Symbol V Supply voltage relative to GND CCINT V Supply voltage relative to GND CCO V Input Reference Voltage REF Input voltage relative to GND V IN ...

Page 27

... Virtex™ 2.5 V Field Programmable Gate Arrays Device Min Max All 2.0 All 1.2 XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 100 XCV800 100 XCV1000 100 XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All All –10 +10 All All 0.25 Note (2) Note (2) 0.15 Units ...

Page 28

Virtex™ 2.5 V Field Programmable Gate Arrays Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power ...

Page 29

... Values apply to all Virtex devices unless otherwise noted. Device Symbol All T IOPI XCV50 T IOPID XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All T IOPLI XCV50 T IOPLID XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All IOCKIQ www.xilinx.com 1-800-255-7778 Virtex™ 2.5 V Field Programmable Gate Arrays ...

Page 30

... A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Module Device Symbol All T /T IOPICK IOICKP XCV50 T /T IOPICKD IOICKPD XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 ...

Page 31

R IOB Input Switching Characteristics Standard Adjustments Description Data Input Delay Adjustments Standard-specific data input delay adjustments Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see IOB Output Switching Characteristics Output delays terminating ...

Page 32

Virtex™ 2.5 V Field Programmable Gate Arrays Description Clock CLK to Pad delay with OBUFT enabled (non-3-state) Clock CLK to Pad high-impedance (1) (synchronous) Clock CLK to valid data on Pad delay, plus enable delay for OBUFT Setup and Hold ...

Page 33

R IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Description Output Delay Adjustments Standard-specific ...

Page 34

Virtex™ 2.5 V Field Programmable Gate Arrays Calculation Function of ioop Capacitance T is the propagation delay from the O Input of the IOB to ioop the pad. The values for T were based on the ...

Page 35

... Description GCLK IOB and Buffer Global Clock PAD to output. Global Clock Buffer I input to O output DS003-3 (v3.2) September 10, 2002 Production Product Specification Virtex™ 2.5 V Field Programmable Gate Arrays Device Symbol -6 XCV50 T 0.10 GSKEWIOB XCV100 0.12 XCV150 0.12 XCV200 0.13 XCV300 ...

Page 36

Virtex™ 2.5 V Field Programmable Gate Arrays I/O Standard Global Clock Input Adjustments Description Data Input Delay Adjustments Standard-specific global clock input delay adjustments Notes: 1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see ...

Page 37

R CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Description Combinatorial Delays 4-input function: F/G inputs to X/Y outputs ...

Page 38

Virtex™ 2.5 V Field Programmable Gate Arrays CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Description Combinatorial ...

Page 39

R CLB SelectRAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active mode Clock CLK to X/Y outputs (WE active mode Shift-Register Mode Clock CLK to X/Y outputs Setup and Hold ...

Page 40

Virtex™ 2.5 V Field Programmable Gate Arrays Block RAM Switching Characteristics Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times before/after Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK Minimum Pulse ...

Page 41

... XCV200 1.0 XCV300 1.0 XCV400 1.0 XCV600 1.0 XCV800 1.0 XCV1000 1.0 Table 2 and Table 3. Symbol Device Min T XCV50 1.5 ICKOF XCV100 1.5 XCV150 1.5 XCV200 1.5 XCV300 1.5 XCV400 1.5 XCV600 1.6 XCV800 1.6 XCV1000 1.7 Table 2 and Table 3 ...

Page 42

Virtex™ 2.5 V Field Programmable Gate Arrays Minimum Clock-to-Out for Virtex Devices With DLL I/O Standard All Devices *LVTTL_S2 5.2 *LVTTL_S4 3.5 *LVTTL_S6 2.8 *LVTTL_S8 2.2 *LVTTL_S12 2.0 *LVTTL_S16 1.9 *LVTTL_S24 1.8 *LVTTL_F2 2.9 *LVTTL_F4 1.7 *LVTTL_F6 1.2 *LVTTL_F8 1.1 ...

Page 43

... A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS003-3 (v3.2) September 10, 2002 Production Product Specification Symbol Device Min T /T XCV50 0.40 / –0.4 PSDLL PHDLL XCV100 0.40 /–0.4 XCV150 0.40 /–0.4 XCV200 0.40 /– ...

Page 44

... Global Clock input signal with the slowest route and heaviest load Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. Module Symbol Device Min T /T XCV50 0 PSFD PHFD XCV100 0 XCV150 0 XCV200 0 XCV300 ...

Page 45

R DLL Timing Parameters All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating ...

Page 46

Virtex™ 2.5 V Field Programmable Gate Arrays Period Tolerance: the allowed input clock period change in nanoseconds. T CLKIN Output Jitter: the difference between an ideal reference clock edge and the actual design. Ideal Period Actual Period Revision History Date ...

Page 47

R Date Version 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New TBCKO values; corrected FG680 package connection ...

Page 48

Virtex™ 2.5 V Field Programmable Gate Arrays Module www.xilinx.com 1-800-255-7778 R DS003-3 (v3.2) September 10, 2002 Production Product Specification ...

Page 49

R DS003-4 (v2.8) July 19, 2002 Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Name Pin GCK0, GCK1, Yes GCK2, GCK3 M0, M1, M2 Yes CCLK Yes PROGRAM Yes DONE Yes INIT No BUSY/ No DOUT D0/DIN, No ...

Page 50

Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Pinout Information Pinout Tables See for updates or additional pinout information. For convenience, www.xilinx.com locations of special-purpose and power-supply pins. Pins not listed are either user I/Os or not connected, depending on ...

Page 51

... XCV800 Within each bank, if input reference voltage is not required, all V pins are general REF I/ Bank 2 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device XCV400 and all smaller devices ...

Page 52

... XCV800 Within each bank, if input reference voltage is not required, all V pins are general REF I/ Bank 5 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device XCV400 and all smaller devices ...

Page 53

... XCV800 Within each bank, if input reference voltage is not required, all V pins are general REF I/ Bank 7 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device XCV400 and all smaller devices ...

Page 54

Virtex™ 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) Pin Name GCK0 GCK1 GCK2 GCK3 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN WRITE CS TDI TDO TMS ...

Page 55

... Bank 2 CCO V , Bank 3 CCO V , Bank 4 CCO V , Bank 5 CCO V , Bank 6 CCO DS003-4 (v2.8) July 19, 2002 Production Product Specification Device BG256 XCV50/100 C10, D6, D15, F4, F17, L3, L18, R4, R17, U6, U15, V10 XCV150/200/300 Same as above K4, P2, P25, AC10, AE14, N/A All D7, D8 All D13, D14 All ...

Page 56

... XCV800 N/A XCV1000 N/A XCV50 A17, B12 XCV100/150 ... + B15 XCV200/300 ... + B17 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A XCV50 C20, J18 XCV100/150 ... + F19 XCV200/300 ... + G18 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A www.xilinx.com 1-800-255-7778 BG352 BG432 A31, L28, L31 ...

Page 57

... N/A XCV800 N/A XCV1000 N/A XCV50 V9, Y3 XCV100/150 ... + W6 AC15, AC18, XCV200/300 ... + V7 ... + AE23 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A XCV50 M2, R3 XCV100/150 ... + T1 R24, Y26, XCV200/300 ... + T3 ... + AD26 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A www.xilinx.com 1-800-255-7778 BG352 BG432 N/A N/A ...

Page 58

... Within each bank, if input reference voltage is not required, all V pins are REF general I/O. GND (1) GND No Connect Notes extra balls (grounded) at package center. Module Device BG256 XCV50 G3, H1 XCV100/150 ... + D1 D26, G26, XCV200/300 ... + B2 ... + E24 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A All ...

Page 59

R Table 4: Virtex Pinout Tables (Fine-Pitch BGA) Pin Name Device GCK0 GCK1 GCK2 GCK3 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN WRITE CS TDI TDO TMS TCK DXN DXP DS003-4 ...

Page 60

... V , Bank 4 CCO V , Bank 5 CCO V , Bank 6 CCO V , Bank 7 CCO V , Bank 0 XCV50 REF (VREF pins are listed XCV100/150 incrementally. Connect XCV200/300 all pins listed for both the required device and XCV400 all smaller devices listed in the same XCV600 package.) Within each bank, if XCV800 ...

Page 61

... XCV600 package.) Within each bank, if XCV800 input reference voltage is not required, all V REF XCV1000 pins are general I/ Bank 3 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device and XCV400 all smaller devices ...

Page 62

... XCV600 package.) Within each bank, if input reference voltage XCV800 is not required, all V REF pins are general I/O. XCV1000 V , Bank 6 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device and XCV400 all smaller devices ...

Page 63

... R Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device V , Bank 7 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device and XCV400 all smaller devices listed in the same XCV600 package.) Within each bank, if ...

Page 64

Virtex™ 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device No Connect XCV800 (No-connect pins are listed incrementally. All pins listed for both the required device and all larger devices listed in ...

Page 65

R Pinout Diagrams The following diagrams, CS144 Pin Function page 17 through FG680 Pin Function illustrate the locations of special-purpose pins on Virtex FPGAs. Table 5 lists the symbols used in these diagrams. The diagrams also show I/O-bank boundaries. Table ...

Page 66

Virtex™ 2.5 V Field Programmable Gate Arrays TQ144 Pin Function Diagram ✳ ✳ ✳ ✳ 3 ✳ ✳ ✳ Bank 0 ✳ ...

Page 67

R PQ240/HQ240 Pin Function Diagram ✳ ✳ ✳ ✳ ✳ ✳ ✳ 7 ✳ ✳ ✳ Bank 7 V ...

Page 68

Virtex™ 2.5 V Field Programmable Gate Arrays BG256 Pin Function Diagram A ✳ r ✳ B ✳ ✳ ✳ ✳ ✳ E ✳ ✳ ✳ F ✳ ✳ ✳ ✳ ✳ J ✳ ✳ ✳ K ...

Page 69

R BG352 Pin Function Diagram ✳ ✳ ✳ ✳ ➉ ✳ ✳ ✳ ✳ F ➀ ✳ ✳ G ✳ ✳ ✳ ➁ ...

Page 70

Virtex™ 2.5 V Field Programmable Gate Arrays BG432 Pin Function Diagram ✳ ✳ ✳ ✳ ✳ ➉ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ...

Page 71

R BG560 Pin Function Diagram ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ...

Page 72

Virtex™ 2.5 V Field Programmable Gate Arrays FG256 Pin Function Diagram Bank Bank Module Bank 0 Bank 1 ...

Page 73

R FG456 Pin Function Diagram G ❅ ✳ ✳ ✳ A ✳ B ✳ ❅ C ❅ Bank 7 D ✳ E ✳ ✳ ✳ ✳ ✳ F ✳ ❅ ✳ ✳ ✳ G ✳ ✳ ✳ H ❅ ✳ ...

Page 74

Virtex™ 2.5 V Field Programmable Gate Arrays FG676 Pin Function Diagram ✳ ✳ ✳ ✳ ✳ ❄ ❄ ✳ R ❄ ❄ r ✳ ✳ ✳ ✳ ✳ ✳ ❄ ...

Page 75

R FG680 Pin Function Diagram Bank ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ 3 ✳ ✳ ✳ ✳ ✳ r ✳ ✳ ✳ ✳ ✳ ✳ R ...

Page 76

Virtex™ 2.5 V Field Programmable Gate Arrays Revision History Date Version 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 ...

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