XC2V500-6FGG256C Xilinx Inc, XC2V500-6FGG256C Datasheet - Page 35
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XC2V500-6FGG256C
Manufacturer Part Number
XC2V500-6FGG256C
Description
IC FPGA VIRTEX-II 500K 256-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V500-6FGG256C
Number Of Labs/clbs
768
Total Ram Bits
589824
Number Of I /o
172
Number Of Gates
500000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
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Part Number
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Price
Company:
Part Number:
XC2V500-6FGG256C
Manufacturer:
XILINX
Quantity:
745
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Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
Each global clock buffer can either be driven by the clock
pad to distribute a clock directly to the device, or driven by
the Digital Clock Manager (DCM), discussed in
Manager (DCM), page
be driven by local interconnects. The DCM has clock out-
put(s) that can be connected to global clock buffer inputs, as
shown in
DS031-2 (v3.5) November 5, 2007
Product Specification
Figure
R
39.
Multiplier Blocks
29. Each global clock buffer can also
Figure 37: Multipliers (2-column, 4-column, and 6-column)
Figure
38.
Digital Clock
Multiplier Blocks
www.xilinx.com
Virtex-II Platform FPGAs: Functional Description
Multiplier Blocks
Figure 38: Virtex-II Clock Pads
Virtex-II
Device
8 clock pads
8 clock pads
DS031_39_101000
DS031_42_022305
Module 2 of 4
27
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