XC4VFX12-11FFG668I Xilinx Inc, XC4VFX12-11FFG668I Datasheet - Page 152
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XC4VFX12-11FFG668I
Manufacturer Part Number
XC4VFX12-11FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-11FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 4: Block RAM
152
ALMOSTEMPTY Flag
Read Error Flag
Full Flag
Write Error Flag
ALMOSTFULL Flag
The ALMOSTEMPTY flag is set when the FIFO contains the number of entries specified by
the ALMOST_EMPTY_OFFSET value (or fewer), warning the user to stop reading. The
ALMOSTEMPTY flag deasserts three clock cycles after the number of entries in the FIFO
becomes greater than the ALMOST_EMPTY_OFFSET value. It is synchronous to RDCLK.
Once the Empty flag has been asserted, any further read attempts will not increment the
read address pointer but will trigger the Read Error flag. The Read Error flag is deasserted
when Read Enable or Empty is deasserted Low. The Read Error flag is synchronous to
RDCLK.
The Full flag is synchronous with WRCLK, and is asserted one WRCLK after there are no
more available entries in the FIFO queue. Because of this latency, it is recommended to use
the ALMOST_FULL signal to stop further writing. When the FIFO is full, the write pointer
will be frozen. The Full flag is deasserted three write clock cycles after any read operation.
Once the Full flag has been asserted, any further write attempts will not increment the
write address pointer but will trigger the Write Error flag. The Write Error flag is
deasserted when Write Enable or Full is deasserted Low. This signal is synchronous to
WRCLK.
The ALMOSTFULL flag is set when the FIFO has the number of available empty spaces
specified by the ALMOST_FULL_OFFSET value or fewer. The ALMOSTFULL flag warns
the user to stop writing. It deasserts when the number of empty spaces in the FIFO is
greater than the ALMOST_FULL_OFFSET value, and is synchronous to WRCLK.
Table 4-11
Table 4-11: Clock Cycle Latency for Flag Assertion and Deassertion
Notes:
1. Depending on the time between read and write clock edges, the ALMOSTEMPTY and ALMOSTFULL
EMPTY
FULL
ALMOST EMPTY
ALMOST FULL
READ ERROR
WRITE ERROR
flags can deassert one cycle later.
Clock Cycle Latency
shows the number of clock cycles to assert or deassert each flag.
(1)
(1)
www.xilinx.com
Standard
0
1
1
1
0
0
Assertion
FWFT
0
1
1
1
0
0
UG070 (v2.6) December 1, 2008
Standard
Virtex-4 FPGA User Guide
3
3
3
3
0
0
Deassertion
FWFT
4
3
3
3
0
0
R
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