XC4VFX12-11FFG668I Xilinx Inc, XC4VFX12-11FFG668I Datasheet - Page 352
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XC4VFX12-11FFG668I
Manufacturer Part Number
XC4VFX12-11FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-11FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 7: SelectIO Logic Resources
352
To build an edge-triggered D-type flip-flop, use the topmost register (OFF1/TFF1). This
register is also the only register that can be configured as a level sensitive latch. The other
two registers (OFF2/TFF2 and OFF3/TFF3) are used to build various output DDR
registers. See
DDR.
The three data registers share a common clock enable (OCE). Similarly, the three 3-state
control registers share a different clock enable (TCE). The clock enable signals are default
active High. If left unconnected, the clock enable pin for the storage element defaults to the
active state.
All registers in OLOGIC have a common clock and synchronous or asynchronous set and
reset (SR and REV signals).
conjunction with REV.
For each storage element in the OLOGIC block, the SRVAL attributes are independent.
Synchronous or asynchronous set/reset (SRTYPE) can not be set individually for each
storage element in an OLOGIC block.
Most of the control signals have optional inverter. Any inverter placed on a control input is
automatically absorbed.
“Output DDR Overview (ODDR),” page 354
www.xilinx.com
Table 7-1
and
Table 7-2
describe the operation of SR in
for further discussion on output
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R
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