XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 109

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Master/Slave Serial Mode Parameters
Clock timing for Slave Serial configuration programming is shown in
Figure
.
Table 47: Master/Slave Serial Mode Timing Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. If no provision is made in the design to adjust the frequency of CCLK, F
CCLK
9. Programming parameters for both Slave and Master modes are given in
Serial DOUT
R
Serial DOUT
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
High time
Low time
Maximum start-up frequency
Maximum frequency
Frequency tolerance, master mode with
respect to nominal
Serial DIN
Serial DIN
(Output)
CCLK
CCLK
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
1
Figure 9: Master Serial Mode Timing Sequence
T
1
Figure 8: Slave Serial Mode Timing Sequence
DSCK
T
DCC
(Figure
(Figure
T
CKDS
2
8)
2
9)
T
CCD
www.xilinx.com
4
References
T
CCH
Figure
1/2
1/2
3
4
5
CC_SERIAL
Figure
T
F
F
T
DSCK
CC_STARTUP
3
CC_SERIAL
8, with Master Serial clock timing shown in
DCC
should not exceed F
Symbol
T
T
T
T
CCO
CCO
CCH
CCL
Table
/T
/T
5
CCD
CKDS
T
CCL
47.
5.0/0.0
5.0/0.0
CC_STARTUP
Value
+45%
–30%
12.0
5.0
5.0
50
66
ds083-3_08_111104
ds083-3_09_111104
(1)
.
MHz, max
MHz, max
Module 3 of 4
ns, max
ns, min
ns, min
ns, min
ns, min
Units
38

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