XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 122

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Table 64: Example Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
Source Synchronous Timing Budgets
This section describes how to use the parameters provided
in the
tion to develop system-specific timing budgets. The follow-
ing analysis provides information necessary for determining
Virtex-II Pro contributions to an overall system timing analy-
sis; no assumptions are made about the effects of
Inter-Symbol Interference or PCB skew.
Virtex-II Pro Transmitter Data-Valid Window (T
T
source-synchronous data bus at the pins of the device and
is calculated as follows:
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include:
2. IFF = Input Flip-Flop
Example Data Input Set-Up and Hold Times
Relative to a Forwarded Clock Input Pin,
Using DCM and Global Clock Buffer.
Values represent an 18-bit bus located in Banks
2, 3, 6, or 7 and grouped to one Horizontal
Global Clock Line. TRACE must be used to
determine the actual values for any given
design.
For situations where clock and data inputs
conform to different standards, adjust the setup
and hold values accordingly using the values
shown in
Standard Adjustments, page
No Delay
Global Clock and IFF
X
Package skew is not included in these measurements.
is the minimum aggregate valid data period for a
T
TCKSKEW
-
-
X
Source-Synchronous Switching Characteristics
= Data Period - [Jitter
CLK0 and CLK180 DCM jitter
Worst-case duty-cycle distortion using CLK0 and CLK180, T
IOB Input Switching Characteristics
R
(3)
Description
+ TPKGSKEW
(2)
with DCM
23.
(1)
+ Duty Cycle Distortion
(4)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
]
(1)
T
PSDCM_0
Symbol
www.xilinx.com
X
(2)
sec-
)
/T
DCD_CLK180
+
PHDCM_0
Notes:
1. Jitter values and accumulation methodology to be provided in
2. This value depends on the clocking methodology used. See
3. This value represents the worst-case clock-tree skew
4. These values represent the worst-case skew between any two
a future release of this document. The absolute period jitter
values found in the
particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.
Note1 for
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
XC2VPX20
XC2VPX70
XC2VP100
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
Table 61
0.18/ 0.36
0.14/ 0.41
0.14/ 0.41
0.29/ 0.25
0.25/ 0.30
0.18/ 0.36
0.18/ 0.37
0.18/ 0.37
0.23/0.39
0.26/0.37
N/A
.
DCM Timing Parameters
7
Speed Grade
0.18/ 0.40
0.13/ 0.42
0.13/ 0.42
0.31/ 0.24
0.26/ 0.29
0.18/ 0.38
0.18/ 0.38
0.18/ 0.38
0.18/ 0.33
0.21/0.42
0.24/0.40
6
0.18/ 0.41
0.12/ 0.44
0.12/ 0.44
0.31/ 0.24
0.27/ 0.29
0.17/ 0.39
0.18/ 0.38
0.18/ 0.38
0.19/ 0.37
0.21/0.42
0.24/0.41
section of the
5
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
51

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