XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 123

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Virtex-II Pro Receiver Data-Valid Window (R
R
a source-synchronous data bus at the pins of the device
and is calculated as follows:
Notes:
1. This parameter indicates the total sampling error of
Revision History
This section records the change history for this module of the data sheet.
DS083 (v4.7) November 5, 2007
Product Specification
X
01/31/02
06/17/02
09/03/02
09/27/02
11/20/02
11/25/02
is the required minimum aggregate valid data period for
Virtex-II Pro DDR input registers across voltage, temperature,
and process. The characterization methodology uses the DCM
to capture the DDR input registers’ edges of operation. These
measurements include:
R
-
Date
X
= [TSAMP
CLK0 and CLK180 DCM jitter in a quiet system
R
Version
(1)
1.0
2.0
2.1
2.2
2.3
2.4
+ TCKSKEW
Initial Xilinx release.
Added section
Updated parametric information in:
Table
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
(2)
Added new Virtex-II Pro family members.
Added 3.3V-vs-2.5V table entries for some parameters.
Added
referencing special information for 3.3V operation. Add footnote for PCI/PCI-X.
Table
Table
Table
Output Voltage Swing.
Table
Table
Table
Table
(except PCI/PCI-X) to 0 pF.
Table
Added timing parameters from speedsfile v1.62.
Added
Added absolute max ratings for 3.3V-vs-2.5V parameters in
Added recommended operating conditions for V
Updated SSTL2 values in
[Table 32
Added
Table
3.75V. Delete cautionary footnotes related to voltage overshoot/undershoot.
Table
Table
Table
Correct max V
Table
1: Correct lower limit of voltage range of V
+ TPKGSKEW
1: Increase Absolute Max Rating for V
2: Delete V
3: Add I
4: Add Typical Quiescent Supply Currents for XC2VP4 and XC2VP7 only
6: Correct I
7: Correct Min/Max V
10: Reformat LVPECL DC Specifications to match Virtex-II data sheet format
12: Correct parameter name from Differential Output Voltage to Single-Ended
16: Add CPMC405CLOCK max frequencies
27: Add footnote regarding serial data rate limitation in -5 part.
36: Add rows for LVTTL, LVCMOS33, and PCI-X.
32: Add LVTTL, LVCMOS33, and PCI-X. Correct all capacitive load values
48: Correct CCLK max frequencies
Table
Source-Synchronous Switching Characteristics
Table
removed in v2.8.]
General Power Supply
43,
10, which contains LVPECL DC specifications.
BATT
IH
X
Pipelined Multiplier Switching
from V
(3)
OL
CCO
)
www.xilinx.com
. Delete I
]
and I
specifications for 2.5V and below operation. Delete footnote
CCO
OH
Table
L
OD
[Table 32
2. This value represents the worst-case clock-tree skew
3. These values represent the worst-case skew between any two
for SSTL2 I. Add rows for LVTTL, LVCMOS33, and PCI-X.
to 3.6V.
specifications for 2.5V and below operation.
, V
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
6. Added SSTL18 values:
-
-
-
These measurements do not include package or clock tree
skew.
OCM
Requirements.
Worst-case duty-cycle distortion
DCM accuracy (phase offset)
DCM phase shift resolution.
Revision
, and V
removed in v2.8.]
ICM
IN
CCO
and V
Characteristics.
IN
, V
and RocketIO footnote to
REF
TS
, V
section.
from –0.3V to –0.5V for 3.3V.
IN
Table
, and V
Table
6,
1.
TS
Table
from 3.6V to
36,
Module 3 of 4
Table
Table
2.
32.
52

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