XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 127

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
DS083 (v4.7) November 5, 2007
Product Specification
11/17/04
03/01/05
06/20/05
Date
R
Version
4.1
4.2
4.3
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Corrected T
(2) requiring use of oversampling techniques in XAPP572 for serial bit rates under
1 Gb/s.
Table
Footnote (2) requiring use of oversampling techniques in XAPP572 for serial bit rates
under 1 Gb/s.
Table
description for F
ranges. Added Footnotes (3) and (4) requiring use of oversampling techniques in
XAPP572 for serial bit rates under 1 Gb/s.
Table
Table
Updated values in
Switching Characteristics
1.90.
Table 1
AVCCAUXRX respectively.
Table
method in Footnote (3).
Table
Table
Table 22
include descriptions, as well as the actual IOSTANDARD attributes (used in the Xilinx
Table
I/O standards in a more logical order.
Table
Table
Table
Table
Figure
Table
oversampling” added to half-rate operation condition for F
Section
to description of V
must be powered on before or with V
ranges.
Table
ICE™ software) for all I/O standards.
Table
Table
Table
F
Table
CC_STARTUP
23: Added Footnote (4) to T
25: Converted bit rate conditions for jitter parameters into four ranges. Added
27: Additional description of “2X oversampling” added to half-speed clock
37: Changed capacitance C
46: Added Min/Max specifications for T
3: Further clarified P
5: Added power-on current specifications for XC2VPX70 device.
22: Changed F
33,
33: Rearranged I/O standards in a more logical order.
34: Added parameter T
35: Changed “Csl” to “C
36: Added footnote defining equivalents for DCI standards.
37: Added Footnotes (2) and (3) to PCI/PCI-X capacitive load (C
44: Added parameter T
47: Added Footnote (1) indicating that F
49: T
12: Added specifications for Differential Input Impedance.
8,
and
Power-On Power Supply Requirements, page
and
Figure
Table
TCKTDO
LOCK
Table
Table
if CCLK frequency is not adjustable.
35,
GGTX
9: Corrected T
from Typ to Max specification. Additional description of “2X
www.xilinx.com
CCINT
2: Corrected VCCAUXTX and VCCAUXRX to AVCCAUXTX and
Virtex-II Pro Performance Characteristics
corrected from a “Min” to a “Max” specification.
23: Changed T
Table
GTOL
. Converted bit rate conditions for jitter parameters into four
ramp-on requirements. Removed requirement that V
36, and
tables, based on values extracted from speedsfile version
RXTX
from ±100 ppm to ±350 ppm.
RPW
BCCS
REF
CCO
(MGT power dissipation) by explaining measurement
” to agree with
PHASE
Table
REF
(Minimum Pulse Width, SR Input).
, CLKA to CLKB Setup Time.
GJTT
/ DOUT to refer to the falling edge of CCLK.
Revision
CCO
for all PCI/PCI-X standards from 0 pF to 10 pF.
bit rate qualifiers from fixed bit rates to bit rate
37: Restructured these I/O-related tables to
indicating an 8B/10B-type bitstream.
.
ICCK
CC_SERIAL
Figure 6
.
5: Added word “monotonically”
should not exceed
and
GCLK
and
Table
, and added Footnote
Virtex-II Pro
37. Rearranged
REF
) values.
Module 3 of 4
CCAUX
56

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