XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 13

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Functional Description: RocketIO X Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the RocketIO X
multi-gigabit transceiver. For an in-depth discussion of the
RocketIO X MGT, including digital and analog design con-
siderations, refer to the
Guide.
RocketIO X Overview
Either eight or twenty RocketIO X MGTs are available on
the XC2VPX20 and XC2VPX70 devices, respectively. The
XC2VPX20 MGT is designed to operate at any baud rate in
the range of 2.488 Gb/s to 6.25 Gb/s per channel. This
includes specific baud rates used by various standards as
listed in
4.25 Gb/s per channel.
The RocketIO X MGT consists of the Physical Media
Attachment (PMA) and Physical Coding Sublayer (PCS).
The PMA contains the 6.25 Gb/s serializer/deserializer
(SERDES), TX/RX buffers, clock generator, and clock
recovery circuitry. The RocketIO X PCS has been signifi-
cantly updated relative to the RocketIO PCS. In addition to
the existing RocketIO PCS features, the RocketIO X PCS
features 64B/66B encoder/decoder/scrambler/descrambler
and SONET compatibility.
PMA
Transmitter Output
The RocketIO X transceiver is implemented in Current
Mode Logic (CML). A CML transmitter output consists of
transistors configured as shown in
positive supply and offers easy interface requirements. In
this configuration, both legs of the driver, VP and VN, sink
current, with one leg always sinking more current than its
complement. The CML output consists of a differential pair
with 50Ω source resistors. The signal swing is created by
switching the current in a common-source differential pair.
DS083 (v4.7) November 5, 2007
Product Specification
Table
Figure 2: CML Output Configuration
R
1. The XC2VPX70 MGT operates at a fixed
CML Output Driver
RocketIO X Transceiver User
V
V
P
N
V
Figure
P
-
V
N
DS083-2_66_052104
=
2. CML uses a
V
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
DATA
www.xilinx.com
See
between the RocketIO X PMA/PCS and the RocketIO
PMA/PCS.
Figure 4, page 3
RocketIO X transceiver and its FPGA interface signals.
Table 1: Communications Standards Supported by
RocketIO X Transceiver
Transmitter Termination
On-chip termination is provided at the transmitter, eliminat-
ing the need for external termination. The output driver and
termination are powered by V
uses a CML approach with 50Ω termination to TXP and
TXN as shown in
Notes:
1.
2. XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
SONET OC-48
PCI Express
Infiniband
XAUI (10-Gb Ethernet)
XAUI
(10-Gb Fibre Channel)
Aurora (Xilinx protocol)
Custom Mode
One channel is considered to be one transceiver.
Table 7, page
Figure 3: RocketIO X Transmit Termination
Mode
Figure
shows a high-level block diagram of the
50Ω
17, for a summary of the differences
3.
(2)
1, 2, 4, 8, 16
TTX
1, 2, 3, 4,...
1, 2, 3, 4,...
Channels
(Lanes)
1, 4, 12
50Ω
at 1.5V. This configuration
1
4
4
(1)
VTTX (1.5V)
TXP
TXN
I/O Bit Rate
2.488 to 6.25
2.488 to 6.25
ug083_34_050704
Module 2 of 4
(Gb/s)
3.1875
2.488
3.125
2.5
2.5
2

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