XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 134

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Table 4: Virtex-II Pro Pin Definitions (Continued)
BREFCLK Pin Definitions (RocketIO Only)
These dedicated clocks use the same clock inputs for all packages:
For detailed information about using BREFCLK/BREFCLK2, including routing considerations and pin numbers for all
package types, refer to Chapter 2, "Digital Design Considerations," in the
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. All dedicated pins (JTAG and configuration) are powered by V
2. Virtex-II Pro X devices XC2VPX20 and XC2VPX70 only. Each BREFCLK(N/P) differential clock input pair takes the place of one
BREFCLKN,
BREFCLKP
VTRXPAD#
VTTXPAD#
GNDA#
RXPPAD#
RXNPAD#
TXPPAD#
TXNPAD#
regular Virtex-II Pro dual-function IO/GCLKx(S/P) pair on each side of the chip (top or bottom). For RocketIO BREFCLK, see section
BREFCLK Pin Definitions (RocketIO Only)
Top
Pin Name
R
BREFCLK2
BREFCLK
(2)
Direction
Output
Output
N
N
Input
Input
Input
Input
Input
Input
P
P
GCLK4S
GCLK5P
GCLK2S
GCLK3P
Differential clock input that clocks the RocketIO X MGTs populating the same side of
the chip (top or bottom). Can also drive DCMs for RocketIO X MGT use.
Receive termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
Transmit termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
Ground for the analog circuitry of the RocketIO multi-gigabit transceiver.
Positive differential receive port of the RocketIO multi-gigabit transceiver.
Negative differential receive port of the RocketIO multi-gigabit transceiver.
Positive differential transmit port of the RocketIO multi-gigabit transceiver.
Negative differential transmit port of the RocketIO multi-gigabit transceiver.
immediately following.
Bottom
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
www.xilinx.com
BREFCLK2
BREFCLK
CCAUX
(independent of the bank V
RocketIO Transceiver User Guide
N
N
P
P
Description
GCLK6P
GCLK7S
GCLK0P
GCLK1S
CCO
voltage).
.
Module 4 of 4
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