XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 29

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Functional Description: Processor Block
This section briefly describes the interfaces and compo-
nents of the Processor Block. The subsequent section,
Functional
beginning on
core features. For an in-depth discussion on both the Pro-
cessor Block and PPC405, see tthe
Reference Guide
Reference Guide
http://www.xilinx.com
Processor Block Overview
Figure 14
Block.
Within the Virtex-II Pro Processor Block, there are four com-
ponents:
Embedded PowerPC 405 RISC Core
The PowerPC 405D5 core is a 0.13 µm implementation of
the IBM PowerPC 405D4 core. The advanced process tech-
nology enables the embedded PowerPC 405 (PPC405)
DS083 (v4.7) November 5, 2007
Product Specification
Processor Block = CPU Core + Interface Logic + CPU-FPGA Interface
Embedded IBM PowerPC 405-D5 RISC CPU core
On-Chip Memory (OCM) controllers and interfaces
Clock/control interface logic
CPU-FPGA Interfaces
Figure 14: Processor Block Architecture
shows the internal architecture of the Processor
R
BRAM
BRAM
Description:
page
CPU-FPGA Interfaces
and the
20, offers a summary of major PPC405
available on the Xilinx website at
.
PPC 405
Interface Logic
Core
Control
PowerPC 405 Processor Block
Embedded PowerPC 405 Core
PowerPC Processor
BRAM
BRAM
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
DS083-2_03a_060701
www.xilinx.com
core to operate at 300+ MHz while maintaining low power
consumption. Specially designed interface logic integrates
the core with the surrounding CLBs, block RAMs, and gen-
eral routing resources. Up to four Processor Blocks can be
available in a single Virtex-II Pro device.
The embedded PPC405 core implements the PowerPC
User Instruction Set Architecture (UISA), user-level regis-
ters, programming model, data types, and addressing
modes for 32-bit fixed-point operations. 64-bit operations,
auxiliary processor operations, and floating-point opera-
tions are trapped and can be emulated in software.
Most of the PPC405 core features are compatible with the
specifications for the PowerPC Virtual Environment
Architecture (VEA) and Operating Environment Architecture
(OEA). They also provide a number of optimizations and
extensions to the lower layers of the PowerPC Architecture.
The full architecture of the PPC405 is defined by the
PowerPC Embedded Environment and PowerPC UISA
documentation, available from IBM.
On-Chip Memory (OCM) Controllers
Introduction
The OCM controllers serve as dedicated interfaces
between the block RAMs in the FPGA fabric (see
Block SelectRAM+ Resources, page
available on the embedded PPC405 core. The OCM signals
on the PPC405 core are designed to provide very quick
access to a fixed amount of instruction and data memory
space. The OCM controller provides an interface to both the
64-bit Instruction-Side Block RAM (ISBRAM) and the 32-bit
Data-Side Block RAM (DSBRAM). The designer can
choose to implement:
One of OCM’s primary advantages is that it guarantees a
fixed latency of execution for a higher level of determinism.
Additionally, it reduces cache pollution and thrashing, since
the cache remains available for caching code from other
memory resources.
Typical applications for DSOCM include scratch-pad mem-
ory, as well as use of the dual-port feature of block RAM to
enable bidirectional data transfer between processor and
FPGA. Typical applications for ISOCM include storage of
interrupt service routines.
Functional Features
Common Features
ISBRAM only
DSBRAM only
Both ISBRAM and DSBRAM
No ISBRAM and no DSBRAM
Separate Instruction and Data memory interface
between processor core and BRAMs in FPGA
Dedicated interface to Device Control Register (DCR)
bus for ISOCM and DSOCM
44) and OCM signals
Module 2 of 4
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