XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 3

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
RocketIO Transceiver Features (All Except XC2VPX20 and XC2VPX70)
PowerPC RISC Processor Block Features (All Except XC2VP2)
Virtex-II Pro Platform FPGA Technology (All Devices)
1. Refer to
DS083 (v4.7) November 5, 2007
Product Specification
Programmable Receiver Equalization
Internal AC Coupling
On-Chip 50Ω Termination
-
Pre- and Post-Driver Serial and Parallel TX-to-RX
Full-Duplex Serial Transceiver (SERDES) Capable of
Baud Rates from 600 Mb/s to 3.125 Gb/s
100 Gb/s Duplex Data Rate (20 Channels)
Monolithic Clock Synthesis and Clock Recovery (CDR)
Fibre Channel, 10G Fibre Channel, Gigabit Ethernet,
10 Gb Attachment Unit Interface (XAUI), and
Infiniband-Compliant Transceivers
8-, 16-, or 32-bit Selectable Internal FPGA Interface
8B /10B Encoder and Decoder (optional)
Embedded 300+ MHz Harvard Architecture Block
Low Power Consumption: 0.9 mW/MHz
Five-Stage Data Path Pipeline
Hardware Multiply/Divide Unit
Thirty-Two 32-bit General Purpose Registers
16 KB Two-Way Set-Associative Instruction Cache
16 KB Two-Way Set-Associative Data Cache
SelectRAM+ Memory Hierarchy
-
-
-
Arithmetic Functions
-
-
Flexible Logic Resources
-
-
-
-
-
High-Performance Clock Management Circuitry
-
Eliminates the need for external termination
resistors
Up to 8 Mb of True Dual-Port RAM in 18 Kb block
SelectRAM+ resources
Up to 1,378 Kb of distributed SelectRAM+
resources
High-performance interfaces to external memory
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Up to 88,192 internal registers/latches with Clock
Enable
Up to 88,192 look-up tables (LUTs) or cascadable
variable (1 to 16 bits) shift registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and Sum-of-Products
support
Internal 3-state busing
Up to twelve Digital Clock Manager (DCM) modules
·
XAPP653
R
Precise clock de-skew
for more information.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
www.xilinx.com
Internal Loopback Modes for Testing Operability
Programmable Comma Detection
-
-
8B/10B and 64B/66B Encoding Blocks
50Ω /75Ω on-chip Selectable Transmit and Receive
Terminations
Programmable Comma Detection
Channel Bonding Support (from 2 to 20 Channels)
Rate Matching via Insertion/Deletion Characters
Four Levels of Selectable Pre-Emphasis
Five Levels of Output Differential Voltage
Per-Channel Internal Loopback Modes
2.5V Transceiver Supply Voltage
Memory Management Unit (MMU)
-
-
Dedicated On-Chip Memory (OCM) Interface
Supports IBM CoreConnect™ Bus Architecture
Debug and Trace Support
Timer Facilities
-
Active Interconnect Technology
-
-
-
SelectIO™-Ultra Technology
-
-
-
-
-
-
Allows for any protocol
Allows for detection of any 10-bit character
64-entry unified Translation Look-aside Buffers (TLB)
Variable page sizes (1 KB to 16 MB)
·
·
16 global clock multiplexer buffers in all parts
Fourth-generation segmented routing structure
Fast, predictable routing delay, independent of
fanout
Deep sub-micron noise immunity benefits
Up to 1,164 user I/Os
Twenty-two single-ended standards and
ten differential standards
Programmable LVCMOS sink/source current (2 mA
to 24 mA) per I/O
XCITE Digitally Controlled Impedance (DCI) I/O
PCI/ PCI-X support
Differential signaling
·
·
·
Flexible frequency synthesis
High-resolution phase shifting
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
On-chip differential termination
Bus LVDS I/O
(1)
Module 1 of 4
2

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