XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 31

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
The Trace port provides instruction execution trace informa-
tion to an external trace tool. The PPC405 core is capable of
back trace and forward trace. Back trace is the tracing of
instructions prior to a debug event while forward trace is the
tracing of instructions after a debug event.
The processor JTAG port and the FPGA JTAG port can be
accessed independently, or the two can be programmati-
cally linked together and accessed via the dedicated FPGA
JTAG pins.
For detailed information on the PPC405 JTAG interface,
please refer to the "JTAG Interface" section of the
405 Processor Block Reference Guide
CoreConnect™ Bus Architecture
The Processor Block is compatible with the CoreConnect™
bus architecture. Any CoreConnect compliant cores includ-
ing Xilinx soft IP can integrate with the Processor Block
through this high-performance bus architecture imple-
mented on FPGA fabric.
The CoreConnect architecture provides three buses for
interconnecting Processor Blocks, Xilinx soft IP, third party
IP, and custom logic, as shown in
Functional Description: Embedded PowerPC 405 Core
This section offers a brief overview of the various functional blocks shown in
Embedded PPC405 Core
The embedded PPC405 core is a 32-bit Harvard architec-
ture processor.
DS083 (v4.7) November 5, 2007
Product Specification
R
Figure 16
PLB Master
PLB Master
Interface
Interface
illustrates its functional blocks:
D-Cache
I-Cache
Array
Array
Cache Units
Instruction
Cache
Cache
Data
Unit
Unit
Controller
Controller
Figure
D-Cache
I-Cache
Figure 16: Embedded PPC405 Core Block Diagram
Instruction
OCM
Data
OCM
15:
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Instruction Shadow
Data Shadow
Unified TLB
(64 Entry)
MMU
(8 Entry)
(4 Entry)
PowerPC
TLB
TLB
www.xilinx.com
High-performance peripherals connect to the high-band-
width, low-latency PLB. Slower peripheral cores connect to
the OPB, which reduces traffic on the PLB, resulting in
greater overall system performance.
For more information, refer to:
http://www-3.ibm.com/chips/techlib/techlib.nfs/productfa
milies/CoreConnect_Bus_Architecture/
Fetch & Decode
Execution Unit (EXU)
Decode
32 x 32
Execution Unit
Fetch
Logic
GPR
and
Processor Local Bus (PLB)
On-Chip Peripheral Bus (OPB)
Device Control Register (DCR) bus
Cache units
Memory Management unit
Fetch Decode unit
System
Core
ALU
Figure 15: CoreConnect Block Diagram
3-Element
(PFB1,
Queue
PFB0,
Fetch
DCD)
MAC
Processor Local Bus
Figure
Instruction
System
Core
Processor
16.
Block
JTAG
Debug Logic
Watchdog)
Timers
Debug
Data
System
Timers
Core
(FIT,
PIT,
DS083-2_01_062001
&
Instruction
Trace
Bridge
DCR Bus
Bus
DCR
Bus
CoreConnect Bus Architecture
Peripheral
On-Chip Peripheral Bus
Core
Peripheral
DS083-2_02a_010202
Module 2 of 4
Core
20

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