XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 33



Manufacturer Part Number
Xilinx Inc
Virtex™-II Pror

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
memory protection. Working with appropriate system-level
software, the MMU provides the following functions:
The MMU can be disabled under software control. If the
MMU is not used, the PPC405 core provides other storage
control mechanisms.
Translation Look-Aside Buffer (TLB)
The Translation Look-Aside Buffer (TLB) is the hardware
resource that controls translation and protection. It consists
of 64 entries, each specifying a page to be translated. The
TLB is fully associative; a given page entry can be placed
anywhere in the TLB. The translation function of the MMU
occurs pre-cache. Cache tags and indexing use physical
Software manages the establishment and replacement of
TLB entries. This gives system software significant flexibility
in implementing a custom page replacement strategy. For
example, to reduce TLB thrashing or translation delays,
software can reserve several TLB entries in the TLB for glo-
bally accessible static mappings. The instruction set pro-
vides several instructions used to manage TLB entries.
These instructions are privileged and require the software
to be executing in supervisor state. Additional TLB instruc-
tions are provided to move TLB entry fields to and from
The MMU divides logical storage into pages. Eight page
sizes (1 KB, 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, and
16 MB) are simultaneously supported, such that, at any
given time, the TLB can contain entries for any combination
of page sizes. In order for a logical to physical translation to
exist, a valid entry for the page containing the logical
address must be in the TLB. Addresses for which no TLB
entry exists cause TLB-Miss exceptions.
To improve performance, four instruction-side and eight
data-side TLB entries are kept in shadow arrays. The
shadow arrays allow single-cycle address translation and
also help to avoid TLB contention between load/store and
instruction fetch operations. Hardware manages the
replacement and invalidation of shadow-TLB entries; no
system software action is required.
Memory Protection
When address translation is enabled, the translation mech-
anism provides a basic level of protection.
DS083 (v4.7) November 5, 2007
Product Specification
Translation of the 4 GB effective address space into
physical addresses
Independent enabling of instruction and data
Page-level access control using the translation
Software control of page replacement strategy
Additional control over protection using zones
Storage attributes for cache policy and speculative
memory access control
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
The Zone Protection Register (ZPR) enables the system
software to override the TLB access controls. For example,
the ZPR provides a way to deny read access to application
programs. The ZPR can be used to classify storage by type;
access by type can be changed without manipulating indi-
vidual TLB entries.
The PowerPC Architecture provides WIU0GE (write-back /
endian) storage attributes that control memory accesses,
using bits in the TLB or, when address translation is dis-
abled, storage attribute control registers.
When address translation is enabled, storage attribute con-
trol bits in the TLB control the storage attributes associated
with the current page. When address translation is disabled,
bits in each storage attribute control register control the
storage attributes associated with storage regions. Each
storage attribute control register contains 32 fields. Each
field sets the associated storage attribute for a 128 MB
memory region.
The embedded PPC405 core contains a 64-bit time base
and three timers, as shown in
The time base counter increments either by an internal sig-
nal equal to the CPU clock rate or by a separate external
timer clock signal. No interrupts are generated when the
time base rolls over. The three timers are synchronous with
the time base.
The PIT is a 32-bit register that decrements at the same rate
as the time base is incremented. The user loads the PIT
register with a value to create the desired delay. When the
register reaches zero, the timer stops decrementing and
generates a PIT interrupt. Optionally, the PIT can be pro-
grammed to auto-reload the last value written to the PIT
register, after which the PIT continues to decrement.
The FIT generates periodic interrupts based on one of four
selectable bits in the time base. When the selected bit
changes from 0 to 1, the PPC405 core generates a FIT
The WDT provides a periodic critical-class interrupt based
on a selected bit in the time base. This interrupt can be used
for system error recovery in the event of software or system
lockups. Users may select one of four time periods for the
interval and the type of reset generated if the WDT expires
twice without an intervening clear from software. If enabled,
the watchdog timer generates a reset unless an exception
handler updates the WDT status bit before the timer has
completed two of the selected timer intervals.
Programmable Interval Timer (PIT)
Fixed Interval Timer (FIT)
Watchdog Timer (WDT)
Module 2 of 4

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