XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 35

no-image

XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Functional Description: FPGA
Input/Output Blocks (IOBs)
Virtex-II Pro I/O blocks (IOBs) are provided in groups of two
or four on the perimeter of each device. Each IOB can be
used as input and/or output for single-ended I/Os. Two IOBs
can be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
Figure
IOB blocks are designed for high-performance I/O, support-
ing 22 single-ended standards, as well as differential sig-
naling with LVDS, LDT, bus LVDS, and LVPECL.
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II Pro IOB blocks feature SelectIO-Ultra inputs and
outputs that support a wide variety of I/O signaling stan-
dards.
(V
dependent on the I/O standard (see
An auxiliary supply voltage (V
regardless of the I/O standard used. For exact supply volt-
age absolute maximum ratings, see
Virtex-II Pro X Platform FPGAs: DC and Switching Charac-
teristics.
All of the user IOBs have fixed-clamp diodes to V
ground. The IOBs are not compatible or compliant with 5V
I/O standards (not 5V-tolerant).
DS083 (v4.7) November 5, 2007
Product Specification
CCINT
18.
Switch
Matrix
Figure 18: Virtex-II Pro Input/Output Tile
In
= 1.5V), output driver supply voltage (V
R
addition
to
the
PAD4
PAD3
PAD2
PAD1
IOB
IOB
IOB
IOB
CCAUX
internal
Table 8
= 2.5V) is required,
Differential Pair
Differential Pair
Virtex-II Pro and
DS083-2_30_010202
supply
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
and
CCO
Table
CCO
voltage
and to
www.xilinx.com
) is
9).
Table 10
trolled Impedance. See
(DCI), page
Table 8: Supported Single-Ended I/O Standards
Notes:
1.
2.
3.
4.
5.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCIX
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III _18
HSTL_IV_18
SSTL2_I
SSTL2_II
SSTL18_I
SSTL18_II
IOSTANDARD
Attribute
Refer to
standards.
For PCI and PCI-X standards, refer to XAPP653.
V
voltage or the voltage seen at the I/O pad. Example: If the pin High
level is 1.5V, connect V
SSTL18_I is not a JEDEC-supported standard.
N/R = no requirement.
CCO
(1)
of GTL or GTLP should not be lower than the termination
lists supported I/O standards with Digitally Con-
(4)
XAPP659
(1)
31.
Output
Note (2)
Note (2)
Note (2)
Note (3)
Note (3)
V
1.5
1.5
1.8
1.8
2.5
3.3
3.3
2.5
1.8
1.5
1.5
1.5
1.8
1.8
2.5
1.8
1.8
CCO
for more details on interfacing to these 3.3V
CCO
to 1.5V.
Digitally Controlled Impedance
Note (2)
Note (2)
Note (2)
Note (3)
Note (3)
Input
V
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
3.3
3.3
2.5
1.8
1.5
CCO
Input
V
0.75
0.75
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
REF
Voltage (V
Termination
Module 2 of 4
Board
0.75
0.75
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.2
1.5
1.5
1.5
0.9
0.9
1.8
1.8
0.9
0.9
TT
24
)

Related parts for XC2VP7-5FFG896I