XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 40

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Some input standards require a user-supplied threshold
voltage (V
configured as V
I/O pins in the bank assume this role.
V
only one V
ever, for correct operation, all V
connected to the external reference voltage source.
The V
device pinout tables. Within a given package, the number of
V
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V
nected to the V
devices, some V
DS083 (v4.7) November 5, 2007
Product Specification
REF
REF
Figure 24: I/O Banks: Wire-Bond Packages (FG)
REF
Figure 25: I/O Banks: Flip-Chip Packages (FF)
pins within a bank are interconnected internally, thus
CCO
and V
pins for the largest device anticipated must be con-
REF
REF
and the V
R
CCO
), and certain user-I/O pins are automatically
voltage can be used within each bank. How-
REF
REF
CCO
pins can vary depending on the size of
voltage and not used for I/O. In smaller
inputs. Approximately one in six of the
Bank 1
Bank 0
Bank 5
pins used in larger devices do not con-
REF
Bank 4
Top View
Top View
pins for each bank appear in the
REF
Bank 0
Bank 5
Bank 1
Bank 4
pins in the bank must be
ug002_c2_014_041403
ds031_66_041403
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
REF
www.xilinx.com
pins
REF
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to V
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bi-directional standards in the same bank:
1. Combining output standards only. Output standards
2. Combining input standards only. Input standards
3. Combining input standards and output standards.
4. Combining bi-directional standards with input or
5. Additional rules for combining DCI I/O standards.
The implementation tools will enforce the above design
rules.
Table 12, page
supplies.
with the same output V
combined in the same bank.
Compatible example:
Incompatible example:
with the same input V
can be combined in the same bank.
Compatible example:
Incompatible example:
Incompatible example:
Input standards and output standards with the same
input V
combined in the same bank.
Compatible example:
Incompatible example:
output standards. When combining bi-directional I/O
with other standards, make sure the bi-directional
standard can meet rules 1 through 3 above.
a. No more than one Single Termination type (input or
b. No more than one Split Termination type (input or
SSTL2_I and LVDS_25 outputs
SSTL2_I (output V
LVCMOS33 (output V
LVCMOS15 and HSTL_IV inputs
LVCMOS15 (input V
LVCMOS18 (input V
HSTL_I_DCI_18 (V
HSTL_IV_DCI_18 (V
LVDS_25 output and HSTL_I input
LVDS_25 output (output V
HSTL_I_DCI_18 input (input V
output) is allowed in the same bank.
Incompatible example:
output) is allowed in the same bank.
Incompatible example:
CCO
HSTL_IV_DCI input and HSTL_III_DCI input
HSTL_I_DCI input and HSTL_II_DCI input
CCO
and output V
30, summarizes all standards and voltage
to permit migration to a larger device.
CCO
CCO
REF
CCO
CCO
CCO
REF
CCO
CCO
= 2.5V) and
= 0.9V) and
and input V
= 1.5V) and
= 1.8V) inputs
= 1.1V) inputs
CCO
requirement can be
= 3.3V) outputs
requirement can be
CCO
= 2.5V) and
= 1.8V)
REF
requirements
Module 2 of 4
29

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