XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 94

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
IOB Input Switching Characteristics Standard Adjustments
Table 33
Table 33: IOB Input Switching Characteristics Standard Adjustments
DS083 (v4.7) November 5, 2007
Product Specification
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
ULVDS (Ultra LVDS), 2.5V
BLVDS (Bus LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI, 2.5V
LVDCI, 1.8V
LVDCI, 1.5V
LVDCI, 2.5V, Half-Impedance
LVDCI, 1.8V, Half-Impedance
LVDCI, 1.5V, Half-Impedance
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
gives all standard-specific data input delay adjustments.
R
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
IOSTANDARD
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
LVDSEXT_25
HSLVDCI_15
HSTL_III_18
HSTL_IV_18
LVPECL_25
HSTL_II_18
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_I_18
ULVDS_25
BLVDS_25
SSTL18_II
Attribute
SSTL18_I
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
LVDS_25
SSTL2_II
HSTL_IV
PCI33_3
PCI66_3
HSTL_III
SSTL2_I
HSTL_II
LDT_25
HSTL_I
LVTTL
GTLP
PCIX
GTL
T
T
T
T
T
Parameter
T
T
T
ILVDCI_DV2_25
ILVDCI_DV2_18
ILVDCI_DV2_15
T
T
T
T
T
T
T
T
T
ILVDSEXT_25
T
T
T
T
T
IHSLVDCI_15
T
IHSTL_IV_18
T
T
IHSTL_III_18
ILVPECL_25
T
T
T
IHSTL_II_18
T
ILVCMOS33
ILVCMOS25
ILVCMOS18
ILVCMOS15
T
T
Timing
IHSTL_I_18
IULVDS_25
IBLVDS_25
T
ISSTL18_II
T
ISSTL18_I
ILVDCI_33
ILVDCI_25
ILVDCI_18
ILVDCI_15
ILVDS_25
T
IHSTL_IV
ISSTL2_II
IPCI33_3
IPCI66_3
T
IHSTL_III
ISSTL2_I
IHSTL_II
ILDT_25
T
IHSTL_I
ILVTTL
IGTLP
IPCIX
IGTL
–0.05
0.07
0.04
0.00
0.29
0.36
0.31
0.33
0.31
0.00
0.31
0.69
0.14
0.15
0.12
0.59
0.63
0.59
0.59
0.57
0.58
0.57
0.55
0.56
0.57
0.62
0.64
0.62
0.64
0.00
0.07
0.13
0.00
0.07
0.13
0.59
-7
Speed Grade
–0.05
0.08
0.05
0.00
0.33
0.41
0.36
0.37
0.36
0.00
0.36
0.80
0.16
0.17
0.13
0.68
0.72
0.68
0.68
0.66
0.67
0.65
0.63
0.64
0.65
0.72
0.73
0.72
0.73
0.00
0.09
0.15
0.00
0.09
0.15
0.68
-6
–0.06
0.09
0.05
0.00
0.36
0.45
0.40
0.41
0.40
0.00
0.40
0.88
0.18
0.19
0.15
0.74
0.79
0.75
0.75
0.72
0.74
0.72
0.69
0.70
0.71
0.79
0.81
0.79
0.81
0.00
0.09
0.17
0.00
0.09
0.17
0.75
-5
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23

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