XC4020E-2HQ208C Xilinx Inc, XC4020E-2HQ208C Datasheet - Page 57

IC FPGA 784 CLB'S 208-HQFP

XC4020E-2HQ208C

Manufacturer Part Number
XC4020E-2HQ208C
Description
IC FPGA 784 CLB'S 208-HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4020E-2HQ208C

Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
160
Number Of Gates
20000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1114

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
XC4020E-2HQ208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4020E-2HQ208C
Manufacturer:
XILINX
0
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In the bitstream generation software, the user can specify
Fast ConfigRate, which, starting several bits into the first
frame, increases the CCLK frequency by a factor of eight.
Figure 53: Master Serial Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
CCLK
2. Master Serial mode timing is based on testing in slave mode.
Low until Vcc is valid.
Serial Data In
Serial DOUT
R
(Output)
(Output)
CCLK
DIN setup
DIN hold
Product Obsolete or Under Obsolescence
n – 3
Description
1
T
DSCK
XC4000E and XC4000X Series Field Programmable Gate Arrays
n
n – 2
1
2
2 T
Symbol
CKDS
n + 1
T
T
DSCK
CKDS
For actual timing values please refer to
Switching Characteristics” on page
serial PROM and slaves are fast enough to support this
data rate. XC2000, XC3000/A, and XC3100A devices do
not support the Fast ConfigRate option.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output after con-
figuration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.
Figure 51 on page 60
The leftmost device is in Master Serial mode.
Master Serial mode is selected by a <000> on the mode
pins (M2, M1, M0).
n – 1
Min
20
0
n + 2
shows a full master/slave system.
n
Max
68. Be sure that the
X3223
“Configuration
Units
ns
ns
6-61
6

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