XC4020E-2HQ208C Xilinx Inc, XC4020E-2HQ208C Datasheet - Page 63

• Manufacturer Part Number: XC4020E-2HQ208C
• Description: IC FPGA 784 CLB'S 208-HQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4020E-2HQ208C

• Number Of Logic Elements/cells: 1862
• Number Of Labs/clbs: 784
• Total Ram Bits: 25088
• Number Of I /o: 160
• Number Of Gates: 20000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1114

Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of
go active within 60 ns after the end of
may not be terminated until RDY/
RDY/BUSY
RS, CS1
WS/CS0
D0-D7
DOUT
Write
CCLK
RDY
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
3. CCLK and DOUT timing is tested in slave mode.
4. T
processing and the phase of the internal timing generator for CCLK.
T
is loaded into the input register before the second-level buffer has started shifting out data
BUSY
BUSY
Effective Write time
(CS0, WS=Low; RS, CS1=High)
DIN setup time
DIN hold time
RDY/BUSY delay after end of
Write or Read
RDY/BUSY active after beginning
of Read
RDY/BUSY Low output (Note 4)
R
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
Product Obsolete or Under Obsolescence
Write to LCA
1 T
Description
T
CA
WTRB
2 T
BUSY
DC
4
XC4000E and XC4000X Series Field Programmable Gate Arrays
WS
Previous Byte D6
has been High for one CCLK period.
. A new write may be asserted immediately after RDY/
3 T
CD
1
2
3
4
7
6
Symbol
6 T
T
T
BUSY
T
T
T
WTRB
BUSY
CA
DC
CD
D7
Min
100
60
0
2
7
D0
Read Status
BUSY
READY
BUSY
Max
60
60
occurs when a new word
9
BUSY
D1
goes Low, but write
WS
4
D2
. RDY/
periods
CCLK
Units
ns
ns
ns
ns
ns
BUSY
RS, CS0
WS, CS1
D7
X6097
6-67
will
6