XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 25
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XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Clock Resources
Global and Regional Clocks
Global Clocking Resources
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Global Clocks
Regional Clocks and I/O Clocks
R
For clocking purposes, each Virtex®-4 device is divided into regions. The number of
regions varies with device size, eight regions in the smallest device to 24 regions in the
largest one.
Each Virtex-4 device has 32 matched-skew global clock lines that can clock all sequential
resources on the whole device (CLB, block RAM, DCMs, and I/O), and also drive logic
signals. Any eight of these 32 global clock lines can be used in any region. Global clock
lines are only driven by a global clock buffer, and can also be used as a clock enable circuit
or a glitch-free multiplexer. It can select between two clock sources, and can also switch
away from a failed clock source, a new feature in the Virtex-4 architecture.
A global clock buffer is often driven by a Digital Clock Manager (DCM) to eliminate the
clock distribution delay, or to adjust its delay relative to another clock. There are more
global clocks than DCMs, but a DCM often drives more than one global clock.
Each region has two “clock capable” regional clock inputs. Each input can differentially or
single-endedly drive regional clocks and I/O clocks in the same region, and also in the
region above or below (i.e., in up to three adjacent regions).
The regional clock buffer can be programmed to divide the incoming clock rate by any
integer number from 1 to 8. This feature, in conjunction with the programmable
serializer/deserializer in the IOB (see
allows source-synchronous systems to cross clock domains without using additional logic
resources.
A third type of clocking resource, I/O clocks, are very fast and serve localized I/O
serializer/deserializer circuits (see
For more detail on how to identify clock regions and the associated components, please use
the PACE tool.
Global clocks are a dedicated network of interconnect specifically designed to reach all
clock inputs to the various resources in an FPGA. These networks are designed to have low
skew and low duty cycle distortion, low power, and increased jitter tolerance. They are
also designed to support very high frequency signals.
www.xilinx.com
Chapter 8, “Advanced SelectIO Logic
Chapter 8, “Advanced SelectIO Logic
Chapter 1
Resources”).
Resources”)
25
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