XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 376
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XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 8: Advanced SelectIO Logic Resources
376
Guidelines for Expanding the Serial-to-Parallel Converter Bit Width
Verilog Instantiation Template to use Width Expansion Feature
1.
2.
3.
4.
5.
6.
The following Verilog code uses the width expansion feature in DDR mode with a
deserialization factor of 1:10.
Both ISERDES modules must be adjacent master and slave pairs.
Both ISERDES modules must be in NETWORKING mode (width expansion is not
available in MEMORY mode).
Set the SERDES_MODE attribute for the master ISERDES to MASTER and the slave
ISERDES to SLAVE (see
The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the
MASTER.
The SLAVE only uses the ports Q3 to Q6 as outputs.
DATA_WIDTH for Master and Slave must match.
//
// Module: serial_parallel_converter
//
// Description: Verilog instantiation template for
// a serial-to-parallel converter function using the
// ISERDES.
//
// Device: Virtex-4 Family
//////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module serial_parallel_converter (
input
input
input
wire
wire
wire
wire
wire
wire [9:0] data_internal;
// Instantiate ISERDES for forwarded clock
ISERDES fwd_clk (
Din,
);
Din;
clk_in;
rst;
iserdes_clkout;
iobclk;
clkdiv;
shiftdata1;
shiftdata2;
clk_in,
rst,
.O(iserdes_clkout),
.Q1(),
.Q2(),
.Q3(),
.Q4(),
.Q5(),
.Q6(),
.SHIFTOUT1(),
www.xilinx.com
“SERDES_MODE
Attribute”).
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R
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