XC4VLX25-11FFG668C Xilinx Inc, XC4VLX25-11FFG668C Datasheet - Page 24

• Manufacturer Part Number: XC4VLX25-11FFG668C
• Description: IC FPGA VIRTEX-4 24K 668-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VLX25-11FFG668C

• Number Of Logic Elements/cells: 24192
• Number Of Labs/clbs: 2688
• Total Ram Bits: 1327104
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• Package: 668FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 24192
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 448
• Ram Bits: 1327104
• For Use With: 807-1004 - DAUGHTER CARD WITH VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668122-1523 - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 122-1490

Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4 inches
of FR4 microstrip trace. Standard termination was used for
all testing. The propagation delay of the 4 inch trace is char-
acterized separately and subtracted from the final measure-
ment, and is therefore not included in the generalized test
setup shown in
Table 31: Output Delay Measurement Methodology
DS302 (v3.7) September 9, 2009
Product Specification
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
FPGA Output
Figure 4: Generalized Test Setup
Figure
Description
4.
V
REF
R
C
(probe capacitance)
REF
REF
V
(voltage level when taking
delay measurement)
MEAS
DS302_05_031708
www.xilinx.com
LVTTL (all)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III_18
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. Parame-
ters V
conditions for each I/O standard. The most accurate predic-
tion of propagation delay in any given application can be
obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
I/O Standard
Attribute
test setup, using values from
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
decrease in delay yields the actual worst-case
propagation delay (clock-to-input) of the PCB trace.
REF
, R
REF
, C
REF
, and V
MEAS
MEAS
R
(Ω)
1M
1M
1M
1M
1M
1M
50
25
25
25
25
25
25
25
25
50
25
50
25
50
25
REF
.
.
MEAS
Table
C
(pF)
REF
10
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
fully describe the test
(2)
(2)
(2)
(2)
(3)
(3)
(1)
31.
V
V
V
V
V
1.65
1.25
0.75
0.75
0.94
2.03
0.94
2.03
0.94
2.03
MEAS
(V)
1.1
0.8
0.9
1.4
0.9
1.0
0.9
REF
REF
REF
REF
V
0.75
0.75
(V)
1.8
3.3
3.3
3.3
1.2
1.5
1.5
1.5
0.9
0.9
REF
0
0
0
0
0
0
0
0
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