XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 16

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

GTP_DUAL Tile Switching Characteristics
Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information.
Table 30: GTP_DUAL Tile Performance
Table 31: Dynamic Reconfiguration Port (DRP) in the GTP_DUAL Tile Switching Characteristics
Table 32: GTP_DUAL Tile Reference Clock Switching Characteristics
X-Ref Target - Figure 5
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
F
F
F
F
Symbol
GTPMAX
GPLLMAX
GPLLMIN
GTPDRPCLK
T
T
F
T
T
T
T
DCREF
PHASE
Symbol
GCLK
LOCK
Symbol
RCLK
FCLK
GJTT
The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to
1 Gb/s.
For reference clock rates above 325 MHz, a duty cycle of 45% to 55% must be maintained.
Measured at the package pin. GTP_DUAL jitter characteristics measured using a clock with specification T
Reference clock frequency range
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Reference clock total jitter, peak-peak
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time
GTP DCLK (DRP clock) maximum frequency
Maximum GTP transceiver data rate
Maximum PLL frequency
Minimum PLL frequency
80%
20%
Description
T
FCLK
(2)
Figure 5: Reference Clock Timing Parameters
(1)
Description
Description
(3)
CLK
20% – 80%
80% – 20%
CLK
CLK
Initial PLL lock
Lock to data after PLL has
locked to the reference clock
T
www.xilinx.com
RCLK
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Conditions
Min
60
40
3.75
200
2.0
1.0
-3
-3
ds202_05_100506
All Speed Grades
Speed Grade
Speed Grade
Typ
200
200
GJTT
50
3.75
175
2.0
1.0
-2
-2
.
Max
350
400
400
200
60
40
3.2
2.0
1.0
150
1
-1
-1
Units
Units
Units
Gb/s
GHz
GHz
MHz
MHz
ms
ps
ps
ps
µs
%
16