XC5VSX35T-1FF665I Xilinx Inc, XC5VSX35T-1FF665I Datasheet - Page 222
XC5VSX35T-1FF665I
Manufacturer Part Number
XC5VSX35T-1FF665I
Description
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-1FF665I
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Total Ram Bits
3096576
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 6: SelectIO Resources
222
X-Ref Target - Figure 6-5
The guidelines when using DCI cascading are as follows:
•
•
•
•
•
The master and slave banks must all reside on the same column (left, center, or right)
on the device.
Master and slave banks must have the same V
DCI I/O banking compatibility rules must be satisfied across all master and slave
banks (for example, only one DCI I/O standard using single termination type is
allowed across all master and slave banks). DCI I/O standard compatibility is not
constrained to one bank when DCI cascading is implemented; it extends across all
master and slave banks.
DCI cascading can span the entire column as long as the above guidelines are met.
Locate adjacent banks. Bank location information is best determined from partgen
generated package files (partgen -v XC5VLX50TFF1136). The resulting package
file with a .pkg extension contains XY I/O location information. The X designator
indicates I/Os in the same column. The Y designator indicates the position of an I/O
within a specific bank. The bank number is also shown. Consecutive Y locations
across bank boundaries show adjacent banks. For example, the XC5VLXT in an
FF1136 package shows bank 11 starting with I/O X0Y159 end ending with I/O
location X0Y120. Bank 13 starts with I/O X0Y119 and ends with X0Y80. Bank 15 starts
Local
Local
Local
Bank
Bank
Bank
To
To
To
(When Cascaded)
(When Cascaded)
To Banks Above
To Banks Below
Figure 6-5: DCI Cascading Supported Over Multiple Banks
www.xilinx.com
DCI
CCO
and V
REF
VRN/VRP
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
(if applicable) voltage.
UG190_6_96_012907
Bank A
Bank B
Bank C
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