XC5VSX35T-3FFG665C Xilinx Inc, XC5VSX35T-3FFG665C Datasheet - Page 89
XC5VSX35T-3FFG665C
Manufacturer Part Number
XC5VSX35T-3FFG665C
Description
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-3FFG665C
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Total Ram Bits
3096576
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX35T-3FFG665C
Manufacturer:
XILINX
Quantity:
133
Company:
Part Number:
XC5VSX35T-3FFG665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- Current page: 89 of 385
- Download datasheet (14Mb)
Phase-Locked Loops (PLLs)
Introduction
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
The clock management tile (CMT) in Virtex-5 FPGAs includes two DCMs and one PLL.
There are dedicated routes within a CMT to couple together various components. Each
block within the tile can be treated separately, however, there exists a dedicated routing
between blocks creating restrictions on certain connections. Using these dedicated routes
frees up global resources for other design elements. Additionally, the use of local routes
within the CMT provides an improved clock path because the route is handled locally,
reducing chances for noise coupling.
The CMT diagram
various clock input sources and the DCM-to-PLL and PLL-to-DCM dedicated routing. The
six (total) PLL output clocks are muxed into a single clock signal for use as a reference clock
to the DCMs. Two output clocks from the PLL can drive the DCMs. These two clocks are
100% independent. PLL output clock 0 could drive DCM1 while PLL output clock 1 could
drive DCM2. Each DCM output can be muxed into a single clock signal for use as a
reference clock to the PLL. Only one DCM can be used as the reference clock to the PLL at
any given time. A DCM can not be inserted in the feedback path of the PLL. Both the PLLs
or DCMs of a CMT can be used separately as stand-alone functions. The outputs from the
PLL are not spread spectrum.
(Figure
www.xilinx.com
3-1) shows a high-level view of the connection between the
Chapter 3
89
Related parts for XC5VSX35T-3FFG665C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX 5 35K 665FFGBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 ES 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD .8K 36MCELL 44-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 72MCRCELL 10NS 44VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 1.6K 72MCELL 64-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CR-II CPLD 64MCELL 44-VQFP
Manufacturer:
Xilinx Inc
Datasheet: