XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 114

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
114
•
•
•
•
•
•
Virtex-5 FPGA block RAM usage rules:
•
•
•
•
•
Table 4-1: Parity Use Sceneries
RAMB18
RAMB18
RAMB18
RAMB18
Primitive
All inputs are registered with the port clock and have a setup-to-clock timing
specification.
All outputs have a read function or a read-during-write function, depending on the
state of the write enable (WE) pin. The outputs are available after the clock-to-out
timing interval. The read-during-write outputs have one of three operating modes:
WRITE_FIRST, READ_FIRST, and NO_CHANGE.
A write operation requires one clock edge.
A read operation requires one clock edge.
All output ports are latched. The state of the output port does not change until the
port executes another read or write operation. The default block RAM output is latch
mode.
The output data path has an optional internal pipeline register. Using the register
mode is strongly recommended. This allows a higher clock rate, however, it adds a
clock cycle latency of one.
The Synchronous Set/Reset (SSR) port cannot be used when the ECC decoder is
enabled (EN_ECC_READ = TRUE).
The setup time of the block RAM address and write enable pins must not be violated.
Violating the address setup time (even if write enable is Low) will corrupt the data
contents of the block RAM.
The block RAM register mode SSR requires REGCE = 1 to reset the output DO register
value. The block RAM array data output latch does not get reset in this mode. The
block RAM latch mode SSR requires the block RAM enable, EN = 1, to reset the
output DO latch value.
Although RAMB18SDP (x36 18k block RAM) and RAMB36SDP (x72 36k block RAM)
are simple dual-port primitives, the true dual-port primitives (RAMB18 and
RAMB36) can be used with one read-only port and one write-only port. For example:
a RAMB18s READ_WIDTH_A = 18, WRITE_WIDTH_B = 9, with WEA = 0 and
WEB = 1 is effectively a simple dual-port block RAM with a smaller port width
having been derived from the true dual-port primitive. Similarly, a ROM function can
be built out of either the true dual-port (RAMB18 or RAMB36) or the simple dual-port
block RAM primitives (RAMB18SDP or RAMB36SDP).
Different read and write port width choices are available when using specific block
RAM primitives. The parity bits are only available for the x9, x18, and x36 port
widths. The parity bits should not be used when the read width is x1, x2, or x4. If the
read width is x1, x2 or x4, the effective write width is x1, x2, x4, x8, x16, or x32.
Similarly, when a write width is x1, x2, or x4, the actual available read width is x1, x2,
x4, x8, x16, or x32 even though the primitive attribute is set to 1, 2, 4, 9, 18, or 36
respectively.
Read Width
1, 2, or 4
1, 2, or 4
Table 4-1
9 or 18
9 or 18
Settings
www.xilinx.com
shows some possible scenarios.
Write Width
1, 2, or 4
1, 2, or 4
9 or 18
9 or 18
Effective Read Width Effective Write Width
Same as setting
Same as setting
Same as setting
8 or 16
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Same as setting
Same as setting
Same as setting
8 or 16