XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 133

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Additional Block RAM Primitives
Block RAM Applications
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Creating Larger RAM Structures
Block RAM SSR in Register Mode
•
In addition to RAMB18 and RAMB36, there are other block RAM primitives available for
specific implementations. RAMB18SDP and RAMB36SDP implement the simple dual-port
mode configurations of the block RAM.
the 18 Kb block RAM configured in simple dual-port mode.
The RAMB36SDP can also be configured for the built-in block RAM ECC. For more
information on RAMB36SDP with the ECC feature, see
Block RAM columns have special routing to create wider/deeper blocks using 36 Kb block
RAMs with minimal routing delays. Wider or deeper RAM structures are achieved with a
smaller timing penalty than is encountered when using normal routing resources.
The Xilinx CORE Generator program offers the designer an easy way to generate wider
and deeper memory structures using multiple block RAM instances. This program outputs
VHDL or Verilog instantiation templates and simulation models, along with an EDIF file
for inclusion in a design.
A block RAM SSR in register mode can be used to control the output register as a true
pipeline register independent of the block RAM. As shown in
be read and written independent of register enable or set/reset. In register mode SSR sets
DO to the SRVAL and data can be read from the block RAM to DBRAM. Data at DBRAM
can be clocked out (DO) on the next cycle. The timing diagrams in
Figure 4-13
X-Ref Target - Figure 4-11
In x72 simple dual-port mode, WE[7:0] is connected to the eight user WE inputs.
REGCE
SSR
EN
DI
show different cases of the SSR operation.
In register mode, the block RAM SSR is disabled
and the SSR pin only sets/resets the output registers.
Figure 4-11: Block RAM SSR in Register Mode
BRAM_RAMEN
BRAM_SSR
Block RAM
www.xilinx.com
Table 4-3, page 121
DBRAM
Additional Block RAM Primitives
Built-in Error Correction, page
shows the ports available for
Figure
Register
Output
Figure 4-12
4-11, block RAM can
ug190_4_28_071707
and
DO
158.
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