XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 176

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
X-Ref Target - Figure 5-4
176
CLK
DX
CX
SR
CE
BX
AX
D6
D5
D4
D3
D2
D1
C6
C5
C4
C3
C2
C1
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
LUT
ROM
LUT
ROM
LUT
ROM
LUT
ROM
O6
O5
O6
O5
O6
O5
O6
O5
Each CLB can contain zero or one SLICEM. Every other CLB column contains a SLICEMs.
In addition, the two CLB columns to the left of the DSP48E columns both contain a SLICEL
and a SLICEM.
Figure 5-4: Diagram of SLICEL
COUT
www.xilinx.com
0/1
CIN
DX
CX
BX
AX
D
C
B
A
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Reset Type
Sync
Async
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
SR REV
SR REV
SR REV
SR REV
Q
Q
Q
Q
UG190_5_04_032606
DMUX
D
DQ
CMUX
C
CQ
BMUX
B
BQ
AMUX
A
AQ