XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 177

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 5-2: Virtex-5 FPGA Logic Resources Available in All CLBs
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
XC5VLX20T
XC5VLX30
XC5VFX30T
XC5VLX30T
XC5VSX35T
XC5VLX50
XC5VLX50T
XC5VSX50T
XC5VFX70T
XC5VLX85
XC5VLX85T
XC5VSX95T
XC5VFX100T
XC5VLX110
XC5VLX110T
XC5VFX130T
XC5VTX150T
XC5VLX155
XC5VLX155T
XC5VFX200T
XC5VLX220
XC5VLX220T
XC5VSX240T
XC5VTX240T
XC5VLX330
XC5VLX330T
Device
CLB/Slice Configurations
Row x Column
CLB Array
160 x 108
160 x 108
240 x 108
240 x 108
120 x 30
120 x 30
120 x 34
160 x 38
120 x 54
120 x 54
160 x 46
160 x 56
160 x 54
160 x 54
200 x 56
200 x 58
160 x 76
160 x 76
240 x 68
240 x 78
240 x 78
Table 5-1
implemented in one of the configurations listed.
all CLBs.
Table 5-1: Logic Resources in One CLB
60 x 26
80 x 30
80 x 38
80 x 30
80 x 34
Notes:
1. SLICEM only, SLICEL does not have distributed RAM or shift registers.
Slices LUTs
2
summarizes the logic resources in one CLB. Each CLB or slice can be
8
6-Input LUTs
Number of
Flip-Flops
122,880
138,240
138,240
149,760
149,760
207,360
207,360
12,480
19,200
20,480
19,200
21,760
28,800
28,800
32,640
44,800
51,840
51,840
58,880
64,000
69,120
69,120
81,920
92,800
97,280
97,280
8
www.xilinx.com
Arithmetic and
Carry Chains
Distributed RAM (Kb)
2
Maximum
1,520
1,240
1,120
1,120
1,580
1,500
1,640
1,640
2,280
2,280
2,280
4,200
2,400
3,420
3,420
210
320
380
320
520
480
480
780
820
840
840
Table 5-2
Distributed RAM
256 bits
shows the available resources in
Register (Kb)
Shift
1140
1140
1140
2100
1200
1710
1710
105
160
190
160
260
240
240
390
410
420
420
760
620
560
560
790
750
820
820
(1)
Shift Registers
CLB Overview
128 bits
Number of
Flip-Flops
122,880
138,240
138,240
149,760
149,760
207,360
207,360
12,480
19,200
20,480
19,200
21,760
28,800
28,800
32,640
44,800
51,840
51,840
58,880
64,000
69,120
69,120
81,920
92,800
97,280
97,280
(1)
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