XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 198

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
X-Ref Target - Figure 5-23
198
SEL D [1:0], DATA D [3:0]
SEL C [1:0], DATA C [3:0]
SEL B [1:0], DATA B [3:0]
SEL A [1:0], DATA A [3:0]
Fast Lookahead Carry Logic
16:1 Multiplexer
Each slice has an F8MUX. F8MUX combines the outputs of F7AMUX and F7BMUX to form
a combinatorial function up to 27 inputs (or a 16:1 MUX). Only one 16:1 MUX can be
implemented in a slice, as shown in
It is possible to create multiplexers wider than 16:1 across more than one SLICEM.
However, there are no direct connections between slices to form these wide multiplexers.
In addition to function generators, dedicated carry logic is provided to perform fast
arithmetic addition and subtraction in a slice. A Virtex-5 FPGA CLB has two separate carry
chains, as shown in
logic, as shown in
The carry chain in the Virtex-5 device is running upward and has a height of four bits per
slice. For each bit, there is a carry multiplexer (MUXCY) and a dedicated XOR gate for
adding/subtracting the operands with a selected carry bits. The dedicated carry path and
SELF7
SELF7
SELF8
Input
Input
Input
Input
CLK
(D[6:1])
(C[6:1])
(B[6:1])
(A[6:1])
Figure 5-23: 16:1 Multiplexer in a Slice
(CLK)
(CX)
(AX)
(BX)
Figure
6
6
6
6
Figure
A[6:1]
A[6:1]
A[6:1]
A[6:1]
LUT
LUT
LUT
LUT
5-2.
www.xilinx.com
5-1. The carry chains are cascadable to form wider add/subtract
O6
O6
O6
O6
SLICE
Figure
F7BMUX
F7AMUX
5-23.
F8MUX
(Optional)
D Q
(BMUX)
(B)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_5_23_050506
16:1 MUX
Output
Registered
Output