XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 209

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Event 1: Shift In
During a write (Shift In) operation, the single-bit content of the register at the address on
the A/B/C/D inputs is changed, as data is shifted through the SRL. The data written to
this register is reflected on the A/B/C/D outputs synchronously, if the address is
unchanged during the clock event. If the A/B/C/D inputs are changed during a clock
event, the value of the data at the addressable output (A/B/C/D outputs) is invalid.
•
•
Clock Event 2: Shift In
•
Clock Event 3: Shift In/Addressable (Asynchronous) READ
All Read operations are asynchronous to the CLK signal. If the address is changed
(between clock events), the contents of the register at that address are reflected at the
addressable output (A/B/C/D outputs) after a delay of length T
through a LUT).
•
•
Clock Event 32: MSB (Most Significant Bit) Changes
At time T
in this case) on the DMUX output of the slice via the MC31 output of LUT A (SRL). This is
also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time T
T
WOSCO
At time T
enabling the SRL for the Write operation that follows.
At time T
and is reflected on the A/B/C/D output after a delay of length T
1. Since the address 0 is specified at clock event 1, the data on the DI input is reflected
at A/B/C/D output, because it is written to register 0.
At time T
and is reflected on the A/B/C/D output after a delay of length T
2. Since the address 0 is still specified at clock event 2, the data on the DI input is
reflected at the D output, because it is written to register 0.
At time T
and is reflected on the A/B/C/D output T
The address is changed (from 0 to 2). The value stored in register 2 at this time is a 0
(in this example, this was the first data shifted in), and it is reflected on the A/B/C/D
output after a delay of length T
after clock event 1.
REG
WS
DS
DS
DS
after clock event 32, the first bit shifted into the SRL becomes valid (logical 0
before clock event 1 the data becomes valid (0) at the DI input of the SRL
before clock event 2, the data becomes valid (1) at the DI input of the SRL
before clock event 3, the data becomes valid (1) at the DI input of the SRL
before clock event 1, the write-enable signal (WE) becomes valid-High,
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ILO
.
REG
time after clock event 3.
CLB / Slice Timing Models
ILO
(propagation delay
REG
REG
after clock event
after clock event
REG
and
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