XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 236

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
236
IOBUFDS
Virtex-5 FPGA SelectIO Attributes/Constraints
Location Constraints
IOSTANDARD Attribute
Figure 6-26
X-Ref Target - Figure 6-26
Access to some Virtex-5 FPGA I/O resource features (e.g., location constraints, input delay,
output drive strength, and slew rate) is available through the attributes/constraints
associated with these features. For more information a Constraints Guide is available on
the Xilinx website with syntax examples and VHDL/Verilog reference code. This guide is
available inside the Software Manuals at:
http://www.support.xilinx.com/support/software_manuals.htm
The location constraint (LOC) must be used to specify the I/O location of an instantiated
I/O primitive. The possible values for the location constraint are all the external port
identifiers (e.g., A8, M5, AM6, etc.). These values are device and package size dependent.
The LOC attribute uses the following syntax in the UCF file:
Example:
The IOSTANDARD attribute is available to choose the values for an I/O standard for all
I/O buffers. The supported I/O standards are listed in
attribute uses the following syntax in the UCF file:
The IOSTANDARD default for single-ended I/O is LVCMOS25, for differential I/Os the
default is LVDS_25.
INST <I/O_BUFFER_INSTANTIATION_NAME> LOC =
"<EXTERNAL_PORT_IDENTIFIER>";
INST MY_IO LOC=R7;
INST <I/O_BUFFER_INSTANTIATION_NAME> IOSTANDARD=”<IOSTANDARD VALUE>”;
Figure 6-26: Differential Input/Output Buffer Primitive (IOBUFDS)
shows the differential input/output buffer primitive.
3-state Input
from FPGA
O (Output)
to FPGA
I (Input)
www.xilinx.com
T
IOBUFDS
+
–
+
–
Table
IOB
IO
ug190_6_23_022806
I/O
to/from
device pad
6-39. The IOSTANDARD
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010