XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 291

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

X-Ref Target - Figure 6-82
X-Ref Target - Figure 6-83
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
Differential SSTL Class II (1.8V)
DCI
External Termination
R 0 = 20
R 0 = 20
DIFF_SSTL18_II
DIFF_SSTL18_II
Figure 6-83: Differential SSTL (1.8V) Class II Unidirectional DCI Termination
Figure 6-82: Differential SSTL (1.8V) Class II Unidirectional Termination
Ω
Ω
V
V
CCO
CCO
Figure 6-82
differential SSTL Class II (1.8V) with unidirectional termination.
Figure 6-83
differential SSTL Class II (1.8V) with unidirectional DCI termination.
= 1.8V
= 1.8V
2R
2R
2R
2R
IOB
IOB
VRP
VRN
VRP
VRN
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
shows a sample circuit illustrating a valid termination technique for
shows a sample circuit illustrating a valid termination technique for
R S = 20Ω
R S = 20Ω
V
V
TT
TT
= 0.9V
= 0.9V
www.xilinx.com
50Ω
50Ω
Z 0
Z 0
Specific Guidelines for I/O Supported Standards
Z 0
Z 0
IOB
V
V
V
V
CCO
CCO
TT
TT
= 0.9V
= 0.9V
2R
2R
2R
2R
= 1.8V
= 1.8V
50Ω
50Ω
VRP
VRN
VRP
VRN
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
IOB
+
–
DIFF_SSTL18_II
ug190_6_77_030506
DIFF_SSTL18_II_DCI
+
–
ug190_6_78_030506
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