XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 329

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 7-10: IODELAY Attribute Summary
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IDELAY_TYPE
IDELAY_VALUE
ODELAY_VALUE
HIGH_PERFORMANCE_MODE Boolean: FALSE,
SIGNAL_PATTERN
REFCLK_FREQUENCY
DELAY_SRC
IODELAY Attributes
Attribute
Table 7-10
IDELAY_TYPE Attribute
The IDELAY_TYPE attribute sets the type of delay used. The attribute values are
DEFAULT, FIXED, and VARIABLE. When set to DEFAULT, the zero-hold time delay
element is selected. This delay element is used to guarantee non-positive hold times when
global clocks are used without DCMs to capture data (pin-to-pin parameters).
When set to FIXED, the tap-delay value is fixed at the number of taps determined by the
IDELAY_VALUE attribute setting. This value is preset and cannot be changed after
configuration.
When set to VARIABLE, the variable tap delay element is selected. The tap delay can be
incremented by setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0. The
increment/decrement operation is synchronous to C, the input clock signal.
IDELAY_VALUE Attribute
The IDELAY_VALUE attribute specifies the initial number of tap delays. The possible
values are any integer from 0 to 63. The default value is zero. The value of the tap delay
reverts to IDELAY_VALUE when the tap delay is reset. In variable mode this attribute
determines the initial setting of the delay line.
String:
DEFAULT,
FIXED, or
VARIABLE
Integer: 0 to 63
Integer: 0 to 63
TRUE
String: DATA,
CLOCK
Real: 190.0 to
210.0
String: I, O, IO, or
DATAIN
summarizes the IODELAY attributes.
Value
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Default Value
DEFAULT
0
0
TRUE
DATA
200
DATAIN
Sets the type of tap delay line. Default delay is
used to guarantee zero hold times, fixed delay is
used to set a static delay value, and variable delay
is used to dynamically adjust the delay value.
Specifies the fixed number of delay taps in fixed
mode or the initial starting number of taps in
variable mode (input path).
Specifies the fixed number of delay taps (output
path).
When TRUE, this attribute reduces the output
jitter. The difference in power consumption is
quantified in the Xilinx Power Estimator tool.
The SIGNAL_PATTERN attribute causes the
timing analyzer to account for the appropriate
amount of delay-chain jitter in the data or clock
path.
IDELAYCTRL reference clock frequency (MHz).
I: IODELAY chain input is IDATAIN
O: IODELAY chain input is ODATAIN
IO: IODELAY chain input is IDATAIN and
ODATAIN (controlled by T)
DATAIN: IODELAY chain input is DATAIN
Input/Output Delay Element (IODELAY)
Description
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