XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 334

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-11
334
CLK
CLK
Q1
Q2
D1
D2
T1
T2
Figure 7-11:
ODDR
ODDR
IDDR
Two cases that use the bidirectional IODELAY functionality are important for a given I/O
pin. The first case uses bidirectional IODELAY when the I/O is an output being switched
to an input.
set by the TSCONTROL net coming from the ODDR flip-flop. This controls the selection of
MUXes E and F for the IOB input path and IDELAY_VALUE, respectively. Additionally,
the OBUF is 3-stated.
IODELAY and IOB in Input Mode when 3-state is Disabled
Figure 7-11
DATAOUT
ODATAIN
IODELAY
Delay
Chain
shows the IOB and IODELAY moving toward the input mode as
www.xilinx.com
TSCONTROL
MUX E
MUX F
T
ODELAY_VALUE
IDELAY_VALUE
ODATAIN
IDATAIN
OBUF
IBUF
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
IODELAY_02_082107
PAD