XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 342

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
342
Instantiating IDELAYCTRL with Location (LOC) Constraints
The most efficient way to use the IDELAYCTRL module is to define and lock down the
placement of every IDELAYCTRL instance used in a design. This is done by instantiating
the IDELAYCTRL instances with location (LOC) constraints. The user must define and
lock placement of all ISERDES and IDELAY components using the delay element.
(IDELAY_TYPE attribute set to FIXED or VARIABLE). Once completed, IDELAYCTRL
sites can be chosen and LOC constraints assigned. Xilinx strongly recommends using
IDELAYCTRL with a LOC constraint. When not using an IDELAY (with IDELAY_TYPE in
FIXED or VARIABLE mode) do not assign a LOC constraint to the IDELAYCTRL for that
clock region.
Location Constraints
Each IDELAYCTRL module has XY location coordinates (X:row, Y:column). To constrain
placement, IDELAYCTRL instances can have LOC properties attached to them. The
naming convention for IDELAYCTRL placement coordinates is different from the
convention used in naming CLB locations. This allows LOC properties to transfer easily
from array to array.
There are two methods of attaching LOC properties to IDELAYCTRL instances.
1.
2.
Inserting LOC Constraints in a UCF File
The following syntax is used for inserting LOC constraints in a UCF file.
Embedding LOC Constraints Directly into HDL Design Files
The following syntax is used to embed LOC constraints into a Verilog design file.
In VHDL code, the LOC constraint is described with VHDL attributes. Before it can be
used, the constraint must be declared with the following syntax:
Once declared, the LOC constraint can be specified as:
The Libraries Guide includes VHDL and Verilog use model templates for instantiating
IDELAYCTRL primitives with LOC constraints.
The circuitry that results from instantiating the IDELAYCTRL components is shown in
Figure
Insert LOC constraints in a UCF file
Embed LOC constraints directly into HDL design files
INST "instance_name" LOC=IDELAYCTRL_X#Y#;
// synthesis attribute loc of instance_name is "IDELAYCTRL_X#Y0#";
attribute loc : string;
attribute loc of instance_name:label is "IDELAYCTRL_X#Y0#";
7-20.
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010