XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 35

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
BUFGMUX_CTRL
BUFGMUX_CTRL is a clock buffer with two clock inputs, one clock output, and a select
line. This primitive is based on BUFGCTRL with some pins connected to logic High or
Low.
X-Ref Target - Figure 1-11
BUFGMUX_CTRL uses the S pins as select pins. S can switch anytime without causing a
glitch. The Setup/Hold time on S is for determining whether the output will pass an extra
pulse of the previously selected clock before switching to the new clock. If S changes as
shown in
to Low, then the output will not pass an extra pulse of I0. If S changes following the hold
time for S, then the output will pass an extra pulse. If S violates the Setup/Hold
requirements, the output might pass the extra pulse, but it will not glitch. In any case, the
output will change to the new clock within three clock cycles of the slower clock.
The Setup/Hold requirements for S0 and S1 are with respect to the falling clock edge
(assuming INIT_OUT = 0), not the rising edge as for CE0 and CE1.
Switching conditions for BUFGMUX_CTRL are the same as the S pin of BUFGCTRL.
Figure 1-12
X-Ref Target - Figure 1-12
Other capabilities of the BUFGMUX_CTRL primitive are:
•
•
Pre-selection of I0 and I1 input after configuration.
Initial output can be selected as High or Low after configuration.
Figure 1-11
Figure
I1
I0
illustrates the timing diagram for BUFGMUX_CTRL.
S
I 0
I1
O
S
1-12, prior to the setup time T
illustrates the relationship of BUFGMUX_CTRL and BUFGCTRL.
BUFGMUX_CTRL
Figure 1-12: BUFGMUX_CTRL Timing Diagram
Figure 1-11: BUFGMUX_CTRL as BUFGCTRL
www.xilinx.com
T
BCCKO_O
O
S
BCCCK_S
GND
GND
V
V
DD
DD
and before I0 transitions from High
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
T
BCCKO_O
Global Clocking Resources
UG190_1_12_061909
UG190_1_11_052009
O
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