XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 353

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Advanced SelectIO Logic Resources
Introduction
Input Serial-to-Parallel Logic Resources (ISERDES)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
The I/O functionality in Virtex-5 FPGAs is described in
this user guide.
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The ISERDES in Virtex-5 FPGAs is a dedicated serial-to-parallel converter with specific
clocking and logic features designed to facilitate the implementation of high-speed source-
synchronous applications. The ISERDES avoids the additional timing complexities
encountered when designing deserializers in the FPGA fabric.
ISERDES features include:
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Chapter 6
and their compliance with many industry standards.
Chapter 7
or DDR data.
This chapter covers additional resources:
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Dedicated Deserializer/Serial-to-Parallel Converter
The ISERDES deserializer enables high-speed data transfer without requiring the
FPGA fabric to match the input data frequency. This converter supports both single
data rate (SDR) and double data rate (DDR) modes. In SDR mode, the serial-to-parallel
converter creates a 2-, 3-, 4-, 5-, 6-, 7-, or 8-bit wide parallel word. In DDR mode, the
serial-to-parallel converter creates a 4-, 6-, 8-, or 10-bit-wide parallel word.
Bitslip Submodule
The Bitslip submodule allows designers to reorder the sequence of the parallel data
stream going into the FPGA fabric. This can be used for training source-synchronous
interfaces that include a training pattern.
Dedicated Support for Strobe-based Memory Interfaces
ISERDES contains dedicated circuitry (including the OCLK input pin) to handle the
strobe-to-FPGA clock domain crossover entirely within the ISERDES block. This
allows for higher performance and a simplified implementation.
Input serial-to-parallel converters (ISERDES) and output parallel-to-serial
converters (OSERDES) support very fast I/O data rates, and allow the internal
logic to run up to 10 times slower than the I/O.
The Bitslip submodule can re-align data to word boundaries, detected with the
help of a training pattern.
covers the electrical characteristics of input receivers and output drivers,
describes the register structures dedicated for sending and receiving SDR
www.xilinx.com
Chapter 6
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Chapter 8
Chapter 8
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