XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 371

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
OSERDES Primitive
3-State Parallel-to-Serial Conversion
Table 8-5: CLK/CLKDIV Relationship of the Data Parallel-to-Serial Converter
In addition to parallel-to-serial conversion of data, an OSERDES module also contains a
parallel-to-serial converter for 3-state control of the IOB. Unlike data conversion, the
3-state converter can only serialize up to four bits of parallel 3-state signals. The 3-state
converter cannot be cascaded.
The OSERDES primitive is shown in
X-Ref Target - Figure 8-15
Input Data Width Output in SDR
SHIFTIN1
SHIFTIN2
CLK
CLKDIV
D1
D2
D3
D4
D5
D6
OCE
SR
T1
T2
T3
T4
TCE
Mode
2
3
4
5
6
7
8
www.xilinx.com
Figure 8-15: OSERDES Primitive
Output Parallel-to-Serial Logic Resources (OSERDES)
Input Data Width Output in DDR
Figure
OSERDES
8-15.
Primitive
Mode
10
4
6
8
–
–
–
CLK
2X
3X
4X
5X
6X
7X
8X
ug190_8_15_100307
SHIFTOUT1
SHIFTOUT2
TQ
OQ
CLKDIV
X
X
X
X
X
X
X
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